[coreboot] FIRST LINUX BOOT: v3 on alix1c!
Marc Jones
Marc.Jones at AMD.com
Thu Feb 7 21:23:27 CET 2008
ron minnich wrote:
> On Feb 7, 2008 11:27 AM, Marc Jones <Marc.Jones at amd.com> wrote:
>
>
>> You need good settings for the southbridge in your platform dts. You
>> should be able to copy these from v2.
>>
>> /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
>> lpc_serirq_polarity = "0";
>>
>> /* 0:continuous 1:quiet */
>> lpc_serirq_mode = "0";
>>
>> /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
>> enable_gpio_int_route = "0";
>>
>>
>
> Here are the current defaults (recall that the dts can set defaults)
>
> constructor = "cs5536_constructors";
> pciid = "PCI_VENDOR_ID_AMD,PCI_DEVICE_ID_AMD_CS5536_ISA";
>
> /* Interrupt enables for LPC bus. Each bit is an IRQ 0-15. */
> lpc_serirq_enable = "0";
>
> /* LPC IRQ polarity. Each bit is an IRQ 0-15. */
> lpc_serirq_polarity = "0";
>
> /* 0:continuous 1:quiet */
> lpc_serirq_mode = "0";
>
> /* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
> enable_gpio_int_route = "0";
>
> /* 0:IDE 1:FLASH, if you are using NAND flash instead of IDE drive. */
> enable_ide_nand_flash = "0";
>
> /* IDE: enable CS5536 IDE. There may be a different IDE
> controller on board */
> enable_ide = "0";
>
> /* Enable USB Port 4 (0:host 1:device). */
> enable_USBP4_device = "0";
>
> /* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA.
> * See CS5536 - Data Book (pages 380-381).
> */
> enable_USBP4_overcurrent = "0";
>
> /* COM1 settings */
> com1_enable = "0";
> com1_address = "0x3f8";
> com1_irq = "4";
>
> /* COM2 settings */
> com2_enable = "0";
> com2_address = "0x2f8";
> com2_irq = "3";
>
>
Right, so the defaults of 0 would be bad. You need to match the v2
mainboard config.lb for your v3 mainboard dts.
for the alixc1 it should be something like this.
southbridge {
/config/("southbridge/amd/cs5536/dts");
pcipath = "0xf,0";
enabled;
enable_ide = "1";
lpc_serirq_enable = "0x000010da"; /* Interrupt
enables for LPC bus. Each bit is an IRQ 0-15. */
lpc_serirq_polarity = "0x0000EF25"; /* LPC IRQ
polarity. Each bit is an IRQ 0-15. */
lpc_serirq_mode = "1"; /*
0:continuous 1:quiet */
enable_gpio_int_route = "0x0D0C0700"; /* GPIO(0-0x20)
for INT D:C:B:A, 0xFF=none. See virtual PIC spec. */
};
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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