[coreboot] v3

[Carl-Daniel Hailfinger]

I'm sorry.
I just reread my mail and realized the tone didn't come out right. I
wish to apologize if this caused any irritation.

Regards,
Carl-Daniel

On 06.02.2008 01:21, Carl-Daniel Hailfinger wrote:
> On 05.02.2008 23:44, ron minnich wrote:
>   
>> An assumption on v3 going on was that we could run out of ROM, and be
>> fast, since caches are our friend.
>>
>> That assumption is not working out. Here is another possible design.
>>
>> stage 0, running in ROM, turns on CAR and runs initram in the LAR.
>>
>> initram disables car, copies ALL of LAR to top of memory (defined as
>> Top Of Ram - size of LAR)
>>   
>>     
>
> I hope you mean 4G - size of LAR. Otherwise we have to compile a lot of
> code as relocatable or duplicate it. Our boot block will become a very
> bloated blob with PIC and non-PIC mixed and lots of access wrappers.
> (And Segher will explode... ;-))
>
>   
>> initram finds stage2 in LAR, uncompresses to RAM, jumps to it.
>>
>> stage2 finds stage3 in LAR, uncompresses to RAM, runs it.
>>
>> stage3 finds payload in LAR, uncompresses to RAM, runs it.
>>
>> So we go to a chain model instead of call/return.
>>   
>>     
>
> Sorry, but that is horrible.That way every stage has to call lar
> functions and we possibly have to integrate a dynamic linker into v3.
>   

Please disregard the dynamic linker comment.

>> We stop using ROM-based code due to performance problems.
>>     
>
> I like Marc's approach of enabling failsafe settings directly before
> payload execution a lot more. ROM is cacheable as long as we control the
> environment.
>
> But your shadowing idea is definitely an avenue to explore.
>
> Regards,
> Carl-Daniel
>
>   


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