[coreboot] patch: init gx cache earlier.

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Wed Feb 6 01:43:53 CET 2008


On 05.02.2008 00:27, Marc Jones wrote:
> ron minnich wrote:
>> Why can't we shadow?
>
> We could.

Even at the top of the 4G address range? If that is possible, I'd vote
to shadow the bootblock only to save RAM.

Some comments on the patch:

> Cache the ROM to speed up stage2 and payload decompression.
>
> Due to some cache coherency snoop problems across PCI GeodeLc needs the ROM cache properties to be write-serialize + cache disabled by runtime.
> Add pre_payload() call to each mainboard as the final coreboot function before the payload is called.
>
> Signed-off by: Marc Jones <marc.jones at amd.com>
>
> Index: coreboot-v3/northbridge/amd/geodelx/geodelxinit.c
> ===================================================================
> --- coreboot-v3.orig/northbridge/amd/geodelx/geodelxinit.c	2008-02-04 13:35:52.000000000 -0700
> +++ coreboot-v3/northbridge/amd/geodelx/geodelxinit.c	2008-02-04 13:36:12.000000000 -0700
> @@ -658,7 +658,7 @@
>  #define SYSMEM_RCONF_WRITETHROUGH	8
>  #define DEVRC_RCONF_DEFAULT		0x21
>  #define ROMBASE_RCONF_DEFAULT		0xFFFC0000
> -#define ROMRC_RCONF_DEFAULT		0x25
> +#define ROMRC_RCONF_DEFAULT		0x04
>   

Maybe keep the 0x25 as ROMRC_RCONF_SAFE?

>  
>  /**
>   * TODO.
> Index: coreboot-v3/mainboard/adl/msm800sev/stage1.c
> ===================================================================
> --- coreboot-v3.orig/mainboard/adl/msm800sev/stage1.c	2008-02-04 15:41:14.000000000 -0700
> +++ coreboot-v3/mainboard/adl/msm800sev/stage1.c	2008-02-04 15:50:04.000000000 -0700
> @@ -53,3 +53,15 @@
>  	cs5536_disable_internal_uart();
>  	w83627hf_enable_serial(0x2e, SERIAL_DEV, SERIAL_IOBASE);
>  }
> +
> +void pre_payload(void)
> +{
> +	struct msr msr;
> +
> +	/* Set ROM cache properties for runtime. */
> +	msr = rdmsr(CPU_RCONF_DEFAULT);
> +	msr.hi &= ~(0xFF << 24);	// clear ROMRC
> +	msr.hi |= 0x25 << 24;		// set WS, CD, WP
>   

Use ROMRC_RCONF_SAFE instead of 0x25?

> +	wrmsr(CPU_RCONF_DEFAULT, msr);
> +	banner(BIOS_DEBUG, "pre_payload: done");
> +}


pre_payload() is not board specific, but Geode LX-specific.
geodelxinit.c may be a more appropriate location.


Regards,
Carl-Daniel




More information about the coreboot mailing list