[coreboot] patch: init gx cache earlier.
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Mon Feb 4 10:48:41 CET 2008
Hi Ron,
I really like it. One minor typo in arch/x86/Makefile, rest looks very good.
Regards,
Carl-Daniel
On 04.02.2008 06:44, ron minnich wrote:
> This change moves the geodelxinit code from stage2 to stage1, which in
> turn gets cache turned on much sooner. The system boots a bit faster.
>
> We're still far too slow, perhaps because we are not caching ROM?
>
> Index: arch/x86/Makefile
> Add ../../northbridge/amd/geodelx/geodelxinit.o object
> Index: arch/x86/geodelx/geodelxinit.c
> add sizeram function.
> Index: arch/x86/geodelx/stage1.c
> add called to northbridge_init_early()
> Index: northbridge/amd/geodelx/Makefile
> remove geodelxinit.o object
> remove sizeram function.
> Index: northbridge/amd/geodelx/geodelx.c
> remove call to northbridge_init_early()
Compile tested, no new warnings, no new errors.
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Index: northbridge/amd/geodelx/geodelx.c
> ===================================================================
> --- northbridge/amd/geodelx/geodelx.c (revision 571)
> +++ northbridge/amd/geodelx/geodelx.c (working copy)
> @@ -142,49 +142,6 @@
> };
>
> /**
> - * Size up ram.
> - *
> - * All we need to do here is read the MSR for DRAM and grab out the sizing
> - * bits. Note that this code depends on initram having run. It uses the MSRs,
> - * not the SPDs, and the MSRs of course are set up by initram.
> - *
> - * @return TODO
> - */
> -int sizeram(void)
> -{
> - struct msr msr;
> - int sizem = 0;
> - u32 dimm;
> -
> - /* Get the RAM size from the memory controller as calculated
> - * and set by auto_size_dimm().
> - */
> - msr = rdmsr(MC_CF07_DATA);
> - printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi,
> - msr.lo);
> -
> - /* DIMM 0 */
> - dimm = msr.hi;
> - /* Installed? */
> - if ((dimm & 7) != 7) {
> - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
> - sizem = 4 << ((dimm >> 12) & 0x0F);
> - }
> -
> - /* DIMM 1 */
> - dimm = msr.hi >> 16;
> - /* Installed? */
> - if ((dimm & 7) != 7) {
> - /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
> - sizem += 4 << ((dimm >> 12) & 0x0F);
> - }
> -
> - printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
> -
> - return sizem;
> -}
> -
> -/**
> * Currently not set up.
> *
> * @param dev The nortbridge device.
> @@ -317,7 +274,7 @@
>
> printk(BIOS_SPEW, ">> Entering northbridge.c: %s\n", __FUNCTION__);
>
> - northbridge_init_early();
> +// northbridge_init_early();
> chipsetinit();
>
> setup_realmode_idt();
> Index: northbridge/amd/geodelx/geodelxinit.c
> ===================================================================
> --- northbridge/amd/geodelx/geodelxinit.c (revision 571)
> +++ northbridge/amd/geodelx/geodelxinit.c (working copy)
> @@ -25,7 +25,6 @@
> #include <amd_geodelx.h>
>
> /* Function prototypes */
> -extern int sizeram(void);
>
> struct gliutable {
> unsigned long desc_name;
> @@ -142,6 +141,49 @@
> }
>
> /**
> + * Size up ram.
> + *
> + * All we need to do here is read the MSR for DRAM and grab out the sizing
> + * bits. Note that this code depends on initram having run. It uses the MSRs,
> + * not the SPDs, and the MSRs of course are set up by initram.
> + *
> + * @return TODO
> + */
> +int sizeram(void)
> +{
> + struct msr msr;
> + int sizem = 0;
> + u32 dimm;
> +
> + /* Get the RAM size from the memory controller as calculated
> + * and set by auto_size_dimm().
> + */
> + msr = rdmsr(MC_CF07_DATA);
> + printk(BIOS_DEBUG, "sizeram: _MSR MC_CF07_DATA: %08x:%08x\n", msr.hi,
> + msr.lo);
> +
> + /* DIMM 0 */
> + dimm = msr.hi;
> + /* Installed? */
> + if ((dimm & 7) != 7) {
> + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
> + sizem = 4 << ((dimm >> 12) & 0x0F);
> + }
> +
> + /* DIMM 1 */
> + dimm = msr.hi >> 16;
> + /* Installed? */
> + if ((dimm & 7) != 7) {
> + /* 1:8MB, 2:16MB, 3:32MB, 4:64MB, ... 7:512MB, 8:1GB */
> + sizem += 4 << ((dimm >> 12) & 0x0F);
> + }
> +
> + printk(BIOS_DEBUG, "sizeram: sizem 0x%xMB\n", sizem);
> +
> + return sizem;
> +}
> +
> +/**
> * Set up the system memory registers, i.e. memory that can be used
> * for non-VSM (or SMM) purposes.
> *
> Index: northbridge/amd/geodelx/Makefile
> ===================================================================
> --- northbridge/amd/geodelx/Makefile (revision 571)
> +++ northbridge/amd/geodelx/Makefile (working copy)
> @@ -22,7 +22,6 @@
> ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
>
> STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
> - $(obj)/northbridge/amd/geodelx/geodelxinit.o \
> $(obj)/northbridge/amd/geodelx/vsmsetup.o
>
> endif
> Index: arch/x86/geodelx/stage1.c
> ===================================================================
> --- arch/x86/geodelx/stage1.c (revision 571)
> +++ arch/x86/geodelx/stage1.c (working copy)
> @@ -55,6 +55,7 @@
> */
> void disable_car(void)
> {
> + extern void northbridge_init_early(void);
> int i;
>
> for (i = 0; i < ARRAY_SIZE(msr_table); i++)
> @@ -67,5 +68,6 @@
> __asm__ __volatile__("cld; rep movsl" ::"D" (DCACHE_RAM_BASE), "S" (DCACHE_RAM_BASE), "c" (DCACHE_RAM_SIZE/4): "memory");
> __asm__ __volatile__ ("wbinvd\n");
> banner(BIOS_DEBUG, "Disable_car: done wbinvd");
> + northbridge_init_early();
> banner(BIOS_DEBUG, "disable_car: done");
> }
> Index: arch/x86/Makefile
> ===================================================================
> --- arch/x86/Makefile (revision 571)
> +++ arch/x86/Makefile (working copy)
> @@ -117,6 +117,7 @@
> ifeq ($(CONFIG_CPU_AMD_GEODELX),y)
> STAGE0_CAR_OBJ = geodelx/stage0.o
> STAGE0_ARCH_X86_OBJ += geodelx/stage1.o
> + STAGE0_ARCH_X86_OBJ += ../..//northbridge/amd/geodelx/geodelxinit.o
>
Shouldn't this have only one slash before northbridge, like this:
+ STAGE0_ARCH_X86_OBJ += ../../northbridge/amd/geodelx/geodelxinit.o
> else
> STAGE0_CAR_OBJ = stage0_i586.o
> endif
>
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