[coreboot] ASUS M2N-SLI Deluxe

Paul Menzel paulepanter at users.sourceforge.net
Tue Dec 30 15:56:37 CET 2008


Dear Christian,


Am Dienstag, den 30.12.2008, 15:27 +0100 schrieb Christian Ruppert:

> here is 'lspci -tvnn'.
> additional cards are marked with PCIE CARD at the begin of line, rest
> should be onboard.
> i hope it help :)
> 
> -[0000:00]-+-00.0  nVidia Corporation MCP55 Memory Controller [10de:0369]
>            +-01.0  nVidia Corporation MCP55 LPC Bridge [10de:0360]
>            +-01.1  nVidia Corporation MCP55 SMBus [10de:0368]
>            +-02.0  nVidia Corporation MCP55 USB Controller [10de:036c]
>            +-02.1  nVidia Corporation MCP55 USB Controller [10de:036d]
>            +-04.0  nVidia Corporation MCP55 IDE [10de:036e]
>            +-05.0  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-05.1  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-05.2  nVidia Corporation MCP55 SATA Controller [10de:037f]
>            +-06.0-[0000:01]----0b.0  Texas Instruments TSB43AB22/A
> IEEE-1394a-2000 Controller (PHY/Link) [104c:8023]
>            +-06.1  nVidia Corporation MCP55 High Definition Audio [10de:0371]
>            +-08.0  nVidia Corporation MCP55 Ethernet [10de:0373]
>            +-09.0  nVidia Corporation MCP55 Ethernet [10de:0373]
> PCIE CARD           +-0a.0-[0000:02]----00.0  nVidia Corporation G70
> [GeForce 7600 GT] [10de:0391]
>            +-0e.0-[0000:03]--
> PCIE CARD           +-0f.0-[0000:04]----00.0  nVidia Corporation G70
> [GeForce 7600 GT] [10de:0391]
>            +-18.0  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> HyperTransport Technology Configuration [1022:1100]
>            +-18.1  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> Address Map [1022:1101]
>            +-18.2  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> DRAM Controller [1022:1102]
>            \-18.3  Advanced Micro Devices [AMD] K8 [Athlon64/Opteron]
> Miscellaneous Control [1022:1103]

Thank you. I guess you are referring to [1].

Is it possible that you can test patches to complete the port?


Thanks,

Paul


[1] http://www.coreboot.org/pipermail/coreboot/2007-October/026410.html
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