[coreboot] r1088 - in coreboot-v3: arch/x86 arch/x86/amd/k8 include/arch/x86 mainboard/amd/dbm690t mainboard/amd/serengeti mainboard/gigabyte/m57sli

[svn at coreboot.org]

Author: cozzie
Date: 2008-12-30 08:02:52 +0100 (Tue, 30 Dec 2008)
New Revision: 1088

Modified:
   coreboot-v3/arch/x86/amd/k8/stage1.c
   coreboot-v3/arch/x86/stage1_mtrr.c
   coreboot-v3/include/arch/x86/mtrr.h
   coreboot-v3/mainboard/amd/dbm690t/Makefile
   coreboot-v3/mainboard/amd/serengeti/Makefile
   coreboot-v3/mainboard/gigabyte/m57sli/Makefile
Log:
Fix breakage of k8 targets caused by r1085. Thanks to Myles Watson for 
tracking down the offending commit.

Signed-off-by: Corey Osgood <corey.osgood at gmail.com>
Acked-by: Peter Stuge <peter at stuge.se>



Modified: coreboot-v3/arch/x86/amd/k8/stage1.c
===================================================================
--- coreboot-v3/arch/x86/amd/k8/stage1.c	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/arch/x86/amd/k8/stage1.c	2008-12-30 07:02:52 UTC (rev 1088)
@@ -35,7 +35,7 @@
  */
 void set_init_ram_access(void)
 {
-	set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
+	stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, MTRR_TYPE_WRBACK);
 }
 
 /**

Modified: coreboot-v3/arch/x86/stage1_mtrr.c
===================================================================
--- coreboot-v3/arch/x86/stage1_mtrr.c	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/arch/x86/stage1_mtrr.c	2008-12-30 07:02:52 UTC (rev 1088)
@@ -25,7 +25,7 @@
 	wrmsr(MTRRphysMask_MSR(reg), zero);
 }
 
-void set_var_mtrr(
+void stage1_set_var_mtrr(
 	unsigned long reg, unsigned long base, unsigned long size, unsigned long type)
 
 {
@@ -63,7 +63,7 @@
 {
 	/* Enable caching for 0 - 1MB using variable mtrr */
 	disable_cache();
-	set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
+	stage1_set_var_mtrr(0, 0x00000000, CONFIG_CBMEMK << 10, type);
 	enable_cache();
 }
 
@@ -98,7 +98,7 @@
 	/* enable write through caching so we can do execute in place
 	 * on the flash rom.
 	 */
-	set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
+	stage1_set_var_mtrr(1, XIP_ROM_BASE, XIP_ROM_SIZE, MTRR_TYPE_WRBACK);
 #endif
 #endif
 

Modified: coreboot-v3/include/arch/x86/mtrr.h
===================================================================
--- coreboot-v3/include/arch/x86/mtrr.h	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/include/arch/x86/mtrr.h	2008-12-30 07:02:52 UTC (rev 1088)
@@ -35,6 +35,8 @@
 void x86_setup_var_mtrrs(unsigned address_bits);
 void x86_setup_mtrrs(unsigned address_bits);
 int x86_mtrr_check(void);
+void stage1_set_var_mtrr(unsigned long reg, unsigned long base,
+				unsigned long size, unsigned long type);
 
 #endif
 

Modified: coreboot-v3/mainboard/amd/dbm690t/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/dbm690t/Makefile	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/mainboard/amd/dbm690t/Makefile	2008-12-30 07:02:52 UTC (rev 1088)
@@ -26,6 +26,7 @@
 			$(src)/arch/x86/amd/model_fxx/stage1.c \
 			$(src)/northbridge/amd/k8/get_nodes.c \
 			$(src)/northbridge/amd/k8/libstage1.c \
+			$(src)/arch/x86/stage1_mtrr.c
 
 INITRAM_SRC= $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 			$(src)/northbridge/amd/k8/raminit.c \

Modified: coreboot-v3/mainboard/amd/serengeti/Makefile
===================================================================
--- coreboot-v3/mainboard/amd/serengeti/Makefile	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/mainboard/amd/serengeti/Makefile	2008-12-30 07:02:52 UTC (rev 1088)
@@ -30,6 +30,7 @@
 			$(src)/southbridge/amd/amd8111/stage1_smbus.c \
 			$(src)/southbridge/amd/amd8111/stage1_ctrl.c \
 			$(src)/southbridge/amd/amd8111/stage1_enable_rom.c \
+			$(src)/arch/x86/stage1_mtrr.c
 
 STAGE0_DYNAMIC_SRC :=	$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c
 

Modified: coreboot-v3/mainboard/gigabyte/m57sli/Makefile
===================================================================
--- coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-12-23 23:44:39 UTC (rev 1087)
+++ coreboot-v3/mainboard/gigabyte/m57sli/Makefile	2008-12-30 07:02:52 UTC (rev 1088)
@@ -29,6 +29,7 @@
 			$(src)/northbridge/amd/k8/libstage1.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_smbus.c \
 			$(src)/southbridge/nvidia/mcp55/stage1_enable_rom.c \
+			$(src)/arch/x86/stage1_mtrr.c
 
 STAGE0_DYNAMIC_SRC :=	$(obj)/mainboard/$(MAINBOARDDIR)/option_table.c