[coreboot] Asus P5G-MX(945) + Intel E8200

blink at nm.ru blink at nm.ru
Thu Dec 25 18:44:05 CET 2008

Hello, Peter!


   v2: with my patches added, I have problem with second CPU
initialization now (see v2log)

   I can skip 2nd core initialization but it's wrong.

   v3: It's fail on CAR disable stage(asm code) (see v3log)

   boot stops on first asm instruction "    movl    
%[newesp], %%esp

   if first asm instruction is "    call stage1_phase3      

   boot goes on next stage...

   I don't know what's is the problem, mb wrong OS or GCC 
version (I
use Fedora 10)

   Ron M. chaged instruction after "    movl    %[newesp], 
\n" some days ago, so he hasn't such problem...

   2) I'm not sure, but My acked-by line is

   /Acked-by: JonB /

   // JonB

> 1) Hm, this board isn't explicitly supported at the 
> moment, but it
> will
> be interesting to hear about your results are. How do you 
> build
> coreboot for it?
>  2) Thanks for the contribution!
> In the future please send changes in unified diff format 
> and with a
> Signed-off-by line as described on
> http://www.coreboot.org/Development_Guidelines
> Unified diffs are easy to work with and fairly easy to 
> read. The
> easiest way to create a unified diff is to checkout from 
> svn, make
> changes and then run svn diff in the coreboot-v2 checkout 
> directory.
> I've attached a patch with your changes and my signoff, 
> if you send
> an acked-by line I'll commit it.
> //Peter --
> coreboot mailing list: coreboot at coreboot.org
> http://www.coreboot.org/mailman/listinfo/coreboot
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