[coreboot] [PATCH] SeaBIOS - vgahooks improvements

[Rudolf Marek]

Hi Jason,

I'm reconnecting this to correct thread. Maybe you can set your settings for 
this conference to receive individual emails.

> I had added some very similar code on my VX800 port, except the location
> of pci register that get speed of DDR2(mine is 0x90). I add those code
> in both vgahook.c of Seabios and vgabios.c of Coreboot

Do you have the 0x15 0x5f specification? I never succeeded to get it from Bruce.

> Maybe 155f is VGABIOS dependent?  Yesterday, I test two different
> VGABIOS on my VX800 board for my coreboot code. First one is extracted
> from legacy bios on board, which doesn't play with my 155fcallback(s3
> resume fails). Second one (I don't know where it is from), however,
> seems work fine.

Yes seems so. Mine BIOS works also fine without any callback, but OpenChrome 
Drivers would not allow any other resolution than 640x480 complaining about low 
memory bandwidth.

I studied both sides, VGA ROM BIOS and main BIOS Callbacks. It just writes the 
values of ebx from 0x5f18 to scratch registers.

Mine BIOS is:
ruik at ruiktest:~/coreboot-merge-seabios-XP/coreboot-v2/zal$ strings 32301106.pci 
| head
IBM COMPATIBLEBCPOST
03/01/07
PCIR
    VIA TRC63M
*VT3336   Desktop  NoTV
  Ver20

And finally I have one idea for the S3 resume. We do not need to call SeaBIOS 
again, we can jump to real mode, call the c000:0003 and then jump to waking 
vector directly. SeaBIOS will handle this directly for us without any S3 
entrypoint ;)

Rudolf