[coreboot] r3839 - in trunk/coreboot-v2/src: mainboard/amd/dbm690t mainboard/amd/pistachio southbridge/amd/rs690

[svn at coreboot.org]

Author: hailfinger
Date: 2008-12-23 18:20:46 +0100 (Tue, 23 Dec 2008)
New Revision: 3839

Modified:
   trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
   trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
   trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c
Log:
Handle RS690 quirks for 1 GHz noncoherent HyperTransport.
The RS690 chipset has a problem where it will not work with 1 GHz HT
speed unless NB_CFG_Q_F1000_800 bit 0 is set.

Tested, works on my Asus M2A-VM with an 1 GHz HT capable processor.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Bao, Zheng says:
As a matter of fact, both 600Mhz and 1Ghz have their own specific
setting.
This patch has been tested on dbm690t which HT link works on 800Mhz.

Acked-by: Peter Stuge <peter at stuge.se>


Modified: trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2008-12-23 17:16:11 UTC (rev 3838)
+++ trunk/coreboot-v2/src/mainboard/amd/dbm690t/cache_as_ram_auto.c	2008-12-23 17:20:46 UTC (rev 3839)
@@ -210,6 +210,7 @@
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	rs690_htinit();
 	printk_debug("needs_reset=0x%x\n", needs_reset);
 
 

Modified: trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2008-12-23 17:16:11 UTC (rev 3838)
+++ trunk/coreboot-v2/src/mainboard/amd/pistachio/cache_as_ram_auto.c	2008-12-23 17:20:46 UTC (rev 3839)
@@ -213,6 +213,7 @@
 
 	needs_reset = optimize_link_coherent_ht();
 	needs_reset |= optimize_link_incoherent_ht(sysinfo);
+	rs690_htinit();
 	printk_debug("needs_reset=0x%x\n", needs_reset);
 
 	post_code(0x06);

Modified: trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c	2008-12-23 17:16:11 UTC (rev 3838)
+++ trunk/coreboot-v2/src/southbridge/amd/rs690/rs690_early_setup.c	2008-12-23 17:20:46 UTC (rev 3839)
@@ -2,6 +2,7 @@
  * This file is part of the coreboot project.
  *
  * Copyright (C) 2008 Advanced Micro Devices, Inc.
+ * Copyright (C) 2008 Carl-Daniel Hailfinger
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -175,8 +176,9 @@
 	/*
 	 * About HT, it has been done in enumerate_ht_chain().
 	 */
-	device_t k8_f0;
+	device_t k8_f0, rs690_f0;
 	u32 reg;
+	u8 reg8;
 	u8 k8_ht_freq;
 
 	k8_f0 = PCI_DEV(0, 0x18, 0);
@@ -195,7 +197,22 @@
 	************************/
 	reg = pci_read_config32(k8_f0, 0x88);
 	k8_ht_freq = (reg & 0xf00) >> 8;
-	printk_info("rs690_ht_init k8_ht_freq=%x.\n", k8_ht_freq);
+	printk_spew("rs690_htinit k8_ht_freq=%x.\n", k8_ht_freq);
+	rs690_f0 = PCI_DEV(0, 0, 0);
+	reg8 = pci_read_config8(rs690_f0, 0x9c);
+	printk_spew("rs690_htinit NB_CFG_Q_F1000_800=%x\n", reg8);
+	/* For 1000 MHz HT, NB_CFG_Q_F1000_800 bit 0 MUST be set.
+	 * For any other HT frequency, NB_CFG_Q_F1000_800 bit 0 MUST NOT be set.
+	 */
+	if (((k8_ht_freq == 0x6) || (k8_ht_freq == 0xf)) && (!(reg8 & 0x1))) {
+		printk_info("rs690_htinit setting bit 0 in NB_CFG_Q_F1000_800 to use 1 GHz HT\n");
+		reg8 |= 0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	} else if ((k8_ht_freq != 0x6) && (k8_ht_freq != 0xf) && (reg8 & 0x1)) {
+		printk_info("rs690_htinit clearing bit 0 in NB_CFG_Q_F1000_800 to not use 1 GHz HT\n");
+		reg8 &= ~0x1;
+		pci_write_config8(rs690_f0, 0x9c, reg8);
+	}
 }
 
 /*******************************************************
@@ -462,7 +479,6 @@
 		break;
 	}
 
-	rs690_htinit();
 	k8_optimization();
 	rs690_por_init(nb_dev);
 }