[coreboot] [PATCH 2/2] inteltool: Add support for dumping ICH5 registers
Michał Mirosław
mirq-linux at rere.qmqm.pl
Sat Dec 20 18:04:58 CET 2008
Intel ICH5 is very similar to its predecessor - ICH4. There are
small differences are in power-management registers.
Signed-off-by: Michał Mirosław <mirq-linux at rere.qmqm.pl>
Index: util/inteltool/gpio.c
===================================================================
--- util/inteltool/gpio.c (wersja 3826)
+++ util/inteltool/gpio.c (kopia robocza)
@@ -119,6 +119,7 @@
gpio_registers = ich7_gpio_registers;
size = ARRAY_SIZE(ich7_gpio_registers);
break;
+ case PCI_DEVICE_ID_INTEL_ICH5:
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
gpiobase = pci_read_word(sb, 0x58) & 0xfffc;
Index: util/inteltool/inteltool.h
===================================================================
--- util/inteltool/inteltool.h (wersja 3826)
+++ util/inteltool/inteltool.h (kopia robocza)
@@ -37,6 +37,7 @@
#define PCI_DEVICE_ID_INTEL_ICH2 0x2440
#define PCI_DEVICE_ID_INTEL_ICH4 0x24c0
#define PCI_DEVICE_ID_INTEL_ICH4M 0x24cc
+#define PCI_DEVICE_ID_INTEL_ICH5 0x24d0
#define PCI_DEVICE_ID_INTEL_ICH7DH 0x27b0
#define PCI_DEVICE_ID_INTEL_ICH7 0x27b8
#define PCI_DEVICE_ID_INTEL_ICH7M 0x27b9
Index: util/inteltool/powermgt.c
===================================================================
--- util/inteltool/powermgt.c (wersja 3826)
+++ util/inteltool/powermgt.c (kopia robocza)
@@ -21,6 +21,56 @@
#include <stdio.h>
#include "inteltool.h"
+static const io_register_t ich5_pm_registers[] = {
+ { 0x00, 2, "PM1_STS" },
+ { 0x02, 2, "PM1_EN" },
+ { 0x04, 4, "PM1_CNT" },
+ { 0x08, 4, "PM1_TMR" },
+ { 0x0c, 4, "RESERVED" },
+ { 0x10, 4, "PROC_CNT" },
+ { 0x14, 4, "RESERVED" },
+ { 0x18, 4, "RESERVED" },
+ { 0x1c, 4, "RESERVED" },
+ { 0x20, 4, "RESERVED" },
+ { 0x24, 4, "RESERVED" },
+ { 0x28, 4, "GPE0_STS" },
+ { 0x2C, 4, "GPE0_EN" },
+ { 0x30, 4, "SMI_EN" },
+ { 0x34, 4, "SMI_STS" },
+ { 0x38, 2, "ALT_GP_SMI_EN" },
+ { 0x3a, 2, "ALT_GP_SMI_STS" },
+ { 0x3c, 4, "RESERVED" },
+ { 0x40, 2, "MON_SMI" },
+ { 0x42, 2, "RESERVED" },
+ { 0x44, 2, "DEVACT_STS" },
+ { 0x46, 2, "RESERVED" },
+ { 0x48, 2, "DEVTRAP_EN" },
+ { 0x4a, 2, "RESERVED" },
+ { 0x4c, 4, "RESERVED" },
+ { 0x50, 4, "RESERVED" },
+ { 0x54, 4, "RESERVED" },
+ { 0x58, 4, "RESERVED" },
+ { 0x5c, 4, "RESERVED" },
+ /* Here start the TCO registers */
+ { 0x60, 1, "TCO_RLD" },
+ { 0x61, 1, "TCO_TMR" },
+ { 0x62, 1, "TCO_DAT_IN" },
+ { 0x63, 1, "TCO_DAT_OUT" },
+ { 0x64, 2, "TCO1_STS" },
+ { 0x66, 2, "TCO2_STS" },
+ { 0x68, 2, "TCO1_CNT" },
+ { 0x6a, 2, "TCO2_CNT" },
+ { 0x6c, 2, "TCO_MESSAGE" },
+ { 0x6e, 1, "TCO_WDCNT" },
+ { 0x6f, 1, "RESERVED" },
+ { 0x70, 1, "SW_IRQ_GEN" },
+ { 0x71, 1, "RESERVED" },
+ { 0x72, 2, "RESERVED" },
+ { 0x74, 4, "RESERVED" },
+ { 0x78, 4, "RESERVED" },
+ { 0x7c, 4, "RESERVED" },
+};
+
static const io_register_t ich7_pm_registers[] = {
{ 0x00, 2, "PM1_STS" },
{ 0x02, 2, "PM1_EN" },
@@ -154,6 +204,11 @@
printf("\n============= PMBASE ============\n\n");
switch (sb->device_id) {
+ case PCI_DEVICE_ID_INTEL_ICH5:
+ pmbase = pci_read_word(sb, 0x40) & 0xfffc;
+ pm_registers = ich5_pm_registers;
+ size = ARRAY_SIZE(ich5_pm_registers);
+ break;
case PCI_DEVICE_ID_INTEL_ICH7:
case PCI_DEVICE_ID_INTEL_ICH7M:
case PCI_DEVICE_ID_INTEL_ICH7DH:
Index: util/inteltool/rootcmplx.c
===================================================================
--- util/inteltool/rootcmplx.c (wersja 3826)
+++ util/inteltool/rootcmplx.c (kopia robocza)
@@ -42,6 +42,7 @@
case PCI_DEVICE_ID_INTEL_ICH0:
case PCI_DEVICE_ID_INTEL_ICH4:
case PCI_DEVICE_ID_INTEL_ICH4M:
+ case PCI_DEVICE_ID_INTEL_ICH5:
printf("This southbridge does not have RCBA.\n");
return 1;
default:
Index: util/inteltool/inteltool.c
===================================================================
--- util/inteltool/inteltool.c (wersja 3826)
+++ util/inteltool/inteltool.c (kopia robocza)
@@ -40,6 +40,7 @@
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7M, "ICH7-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7, "ICH7" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH7DH, "ICH7DH" },
+ { PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH5, "ICH5" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4M, "ICH4-M" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH4, "ICH4" },
{ PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_ICH2, "ICH2" },
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