[coreboot] Resource Allocation discussion
Myles Watson
mylesgw at gmail.com
Tue Dec 2 19:06:41 CET 2008
Here's the read_resources code from qemu after my latest patch. Is this
what people are thinking? Notice that I explicitly allocate VGA space and
APIC. At the end of the code I'm pasting in a snippet of the log that shows
the resources after they are assigned values.
Thanks,
Myles
static void i440bx_read_resources(struct device *dev)
{
struct resource *res;
u32 tolmk; /* Top of low mem, Kbytes. */
int idx;
/* I/O resource. */
res = new_resource(dev, 0);
res->base = 0x1000UL;
res->limit = 0xFFFFUL;
res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
/* read large mem memory descriptor
for <16 MB read the more detailed small mem descriptor
all values in kbytes */
tolmk = ((inb_cmos(0x35)<<8) |inb_cmos(0x34)) * 64;
if (tolmk <= 16 * 1024) {
tolmk = (inb_cmos(0x31)<<8) |inb_cmos(0x30);
}
printk(BIOS_WARNING, "Using CMOS settings of %d kB RAM.\n", tolmk);
idx = 10;
/* 0 .. 640 kB */
ram_resource(dev, idx++, 0, 640);
/* Hole for VGA (0xA0000-0xAFFFF) graphics and text mode
* graphics (0xB8000-0xBFFFF) */
res = new_resource(dev, IOINDEX_SUBTRACTIVE(0, 0));
res->base = 0xA0000UL;
res->size = 0x20000UL;
res->limit = 0xBFFFUL;
res->flags = IORESOURCE_MEM | IORESOURCE_SUBTRACTIVE |
IORESOURCE_ASSIGNED | IORESOURCE_FIXED;
/* 768 kB .. Systop (in KB) */
ram_resource(dev, idx++, 768, tolmk - 768);
}
static void i440bx_domain_read_resources(struct device *dev)
{
struct resource *res;
/* Initialize the domain's I/O space constraints. */
res = new_resource(dev, 0);
res->base = 0x1000UL;
res->limit = 0xffffUL;
res->flags = IORESOURCE_IO | IORESOURCE_BRIDGE;
/* Initialize the system-wide memory resources constraints. */
res = new_resource(dev, 1);
res->limit = 0xffffffffULL;
res->flags = IORESOURCE_MEM | IORESOURCE_BRIDGE;
/* Reserve space for the APIC. */
res = new_resource(dev, 2);
res->base = 0xfec00000UL;
res->size = 0x100000UL;
res->limit = 0xffffffffULL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;
/* Reserve space for the APIC. */
res = new_resource(dev, 2);
res->base = 0xfee00000UL;
res->size = 0x10000UL;
res->limit = 0xffffffffULL;
res->flags = IORESOURCE_MEM | IORESOURCE_FIXED | IORESOURCE_STORED;
}
Show resources in subtree (root)...After assigning values.
Root Device links 1 child on link 0 cpus
Root Device resource base 1000 size 410 align 8 gran 0 limit ffff flags
80100 index 0
Root Device resource base fc000000 size 2001000 align 25 gran 0 limit
ffffffff flags 40080200 index 1
Root Device resource base 0 size 0 align 0 gran 0 limit ffffffffffffffff
flags 81200 index 2
CPU: 00 links 0 child on link 0 NULL
PCI_DOMAIN: 0000 links 1 child on link 0 domain_0_pci_0_0
PCI_DOMAIN: 0000 resource base 1000 size 410 align 8 gran 0 limit ffff
flags 40080100 index 0
PCI_DOMAIN: 0000 resource base fc000000 size 2001000 align 25 gran 0 limit
ffffffff flags 40080200 index 1
PCI_DOMAIN: 0000 resource base fee00000 size 10000 align 0 gran 0 limit
ffffffff flags a0000200 index 2
PCI: 00:00.0 links 0 child on link 0 NULL
PCI: 00:00.0 resource base 1000 size 0 align 0 gran 0 limit ffff flags
80100 index 0
PCI: 00:00.0 resource base 0 size a0000 align 0 gran 0 limit 0 flags
e0004200 index a
PCI: 00:00.0 resource base a0000 size 20000 align 0 gran 0 limit bfff
flags c0040200 index 10000000
PCI: 00:00.0 resource base c0000 size 6f40000 align 0 gran 0 limit 0
flags e0004200 index b
PCI: 00:01.0 links 0 child on link 0 NULL
PCI: 00:01.1 links 0 child on link 0 NULL
PCI: 00:01.1 resource base 1400 size 10 align 4 gran 4 limit ffff flags
40000100 index 20
PCI: 00:01.3 links 0 child on link 0 NULL
PCI: 00:02.0 links 0 child on link 0 NULL
PCI: 00:02.0 resource base fc000000 size 2000000 align 25 gran 25 limit
ffffffff flags 40001200 index 10
PCI: 00:02.0 resource base fe000000 size 1000 align 12 gran 12 limit
ffffffff flags 40000200 index 14
PCI: 00:03.0 links 0 child on link 0 NULL
PCI: 00:03.0 resource base 1000 size 100 align 8 gran 8 limit ffff flags
40000100 index 10
Phase 4: Setting resources...
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