[coreboot] resource allocation part 2

[Myles Watson]

This patch makes specific devices use the updated resource allocation code.

The changes necessary are:
    1. Remove all calls to compute_allocate_resources.
    2. Read children's resources when yours are read.
    3. Don't store resources except in phase4_set_resources.

northbridge/amd/k8/domain.c:
    A comment for later cleanup efforts.
    Change the resource base from 0x400 to 0x1000 to match the granularity.
    Add the IORESOURCE_BRIDGE flag.
    Read the resources of the grandchildren.
        This should disappear when the domain has the children.
    Update k8_pci_domain_set_resources:
        1. remove compute_allocate_resource call
        2. Change phase4_assign_resources to phase4_set_resources

northbridge/amd/k8/pci.c:

    Remove calls to compute_allocate_resource.
    Make the VGA resource remain visible.
    Stop passing around nodeid so much.
    Remove unneeded #defines

southbridge/amd/amd8132/amd8132_bridge.c:
    Remove NPUML and NPUMB.
    Add a warning for bus disabling.
    Remove bridge_{read|set}_resources (they were there for NPUML)

northbridge/intel/i440bxemulation/i440bx.c:
    Change phase4_assign_resources->phase4_set_resources.

Signed-off-by: Myles Watson <mylesgw at gmail.com>

Thanks,
Myles
-------------- next part --------------
An HTML attachment was scrubbed...
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20081201/503e2cbe/attachment.html>
-------------- next part --------------
A non-text attachment was scrubbed...
Name: specific-resources.diff
Type: text/x-patch
Size: 13904 bytes
Desc: not available
URL: <http://www.coreboot.org/pipermail/coreboot/attachments/20081201/503e2cbe/attachment.diff>