[coreboot] r853 - in coreboot-v3: device include
svn at coreboot.org
svn at coreboot.org
Sun Aug 31 22:39:48 CEST 2008
Author: rminnich
Date: 2008-08-31 22:39:48 +0200 (Sun, 31 Aug 2008)
New Revision: 853
Modified:
coreboot-v3/device/device.c
coreboot-v3/include/lib.h
coreboot-v3/include/spd_ddr2.h
Log:
remaining fixes for log2. Simple prototype added to spd_ddr2.h
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>
Modified: coreboot-v3/device/device.c
===================================================================
--- coreboot-v3/device/device.c 2008-08-31 20:28:21 UTC (rev 852)
+++ coreboot-v3/device/device.c 2008-08-31 20:39:48 UTC (rev 853)
@@ -446,10 +446,10 @@
* resource type specific.
*/
if (bridge->flags & IORESOURCE_IO) {
- min_align = log2(DEVICE_IO_ALIGN);
+ min_align = log2c(DEVICE_IO_ALIGN);
}
if (bridge->flags & IORESOURCE_MEM) {
- min_align = log2(DEVICE_MEM_ALIGN);
+ min_align = log2c(DEVICE_MEM_ALIGN);
}
/* Make certain we have read in all of the resources. */
Modified: coreboot-v3/include/lib.h
===================================================================
--- coreboot-v3/include/lib.h 2008-08-31 20:28:21 UTC (rev 852)
+++ coreboot-v3/include/lib.h 2008-08-31 20:39:48 UTC (rev 853)
@@ -28,7 +28,13 @@
*/
#define ARRAY_SIZE(a) (sizeof(a) / sizeof((a)[0]))
-int log2(unsigned int n);
+/* you have to explicity pick logc2 (ceiling) or log2f (floor)
+ * it is a no-op if you KNOW that your number is a power of 2.
+ * It is important to know what you are doing otherwise.
+ * example: log2c(72) is 7, log2f(72) is 6!
+ */
+int log2c(unsigned int n);
+int log2f(unsigned int n);
void udelay(unsigned int usecs);
void mdelay(unsigned int msecs);
Modified: coreboot-v3/include/spd_ddr2.h
===================================================================
--- coreboot-v3/include/spd_ddr2.h 2008-08-31 20:28:21 UTC (rev 852)
+++ coreboot-v3/include/spd_ddr2.h 2008-08-31 20:39:48 UTC (rev 853)
@@ -86,3 +86,6 @@
#define SPD_TRFC 42 /* add byte 0x40 bit [6:4] , so final val42+ table[((val40>>4) & 0x7)] + (val40 & 1)*256*/
#define SPD_TREF 12
+
+/* prototypes for dealing with spd */
+u8 spd_read_byte(u16 device, u8 address);
More information about the coreboot
mailing list