[coreboot] [PATCH] v3: fix PCI bus scan / device tree interaction

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sat Aug 30 04:38:43 CEST 2008

On 30.08.2008 04:15, Carl-Daniel Hailfinger wrote:
> On 30.08.2008 00:53, Stefan Reinauer wrote:
>> Carl-Daniel Hailfinger wrote:
>>> IFF we only have one top-level PCI Bus (anything else is impossible with
>>> only one Host Bridge) my patch is completely correct. However, IFF there
>>> are multiple independent Host Bridges which do NOT share a PCI bus, we
>>> need to implement a function which iterates over these Host Bridges.  
>> Which happens on non-x86 systems and occasionally can happen on x86 PCIe.

I'd like a lspci -tn for any such system. My x86 PCIe system has 6
buses, but they are all descending from one top-level bus.

> How about this one? Tested on Qemu, fulfills your criteria. (The qemu
> target needs to be fixed, though).

Turns out that the code worked because pci_scan_bus couldn't care less
about what the device tree says about the bus number. It doesn't look at
bus->dev->path.pci_bus.bus which is set in the dts, but it uses
bus->secondary which is not used by the dts at all.
Our PCI device core needs to be changed to accommodate multiple
top-level PCI buses. However, unless such a system turns up in practice,
I'm inclined to keep the code very simple and add a warning
(compile-time or run-time).



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