[coreboot] r825 - in coreboot-v3: . arch/x86

svn at coreboot.org svn at coreboot.org
Wed Aug 27 03:10:27 CEST 2008


Author: hailfinger
Date: 2008-08-27 03:10:27 +0200 (Wed, 27 Aug 2008)
New Revision: 825

Modified:
   coreboot-v3/Kconfig
   coreboot-v3/arch/x86/Makefile
Log:
Enable compilation with -fwhole-program for initram. The setting can be
chosen via Kconfig. Default off.
Depending on the target, this saves between 10% and 20% of initram size.

Compilation still broken for:
- ADL MSM800SEV
- Gigabyte M57SLI

Compilation changed for:
- AMD DB800 (checker doesn't trigger anymore, but we get an unresolved
symbol instead)
- AMD Norwich (same)
(The compilation changes are not bad per se, just a bit misleading. It
seems that gcc 4.2.x is really smart. gcc 4.3.x and later are even
smarter and even fix compilation completely.)

Compilation OK for:
- AMD Serengeti
- Artec DBE61
- Artec DBE62
- PCEngines Alix.1C
- PCEngines Alix.2C3
- 

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>


Modified: coreboot-v3/Kconfig
===================================================================
--- coreboot-v3/Kconfig	2008-08-26 22:12:02 UTC (rev 824)
+++ coreboot-v3/Kconfig	2008-08-27 01:10:27 UTC (rev 825)
@@ -60,6 +60,22 @@
 	help
 	  Enable this option to make coreboot beep upon certain events.
 
+config WHOLE_PROGRAM_COMPILE
+	bool "Enable whole-program optimizations (DANGEROUS)"
+	depends EXPERT && EXPERIMENTAL
+	help
+	  Enable gcc -fwhole-program -combine for select code.
+	  Needs lots of annotation in stage1 and stage2.
+	  Works for initram only.
+	  This increases compile time (no parallel compilation possible
+	  anymore) and compiler memory usage (up to a factor of 20) and
+	  makes debugging really hard.
+
+	  Requires at least gcc 4.2.x, but miscompilations may occur.
+
+	  Say No.
+	  If you are a Gentoo user, say NO!
+
 endmenu
 
 source mainboard/Kconfig

Modified: coreboot-v3/arch/x86/Makefile
===================================================================
--- coreboot-v3/arch/x86/Makefile	2008-08-26 22:12:02 UTC (rev 824)
+++ coreboot-v3/arch/x86/Makefile	2008-08-27 01:10:27 UTC (rev 825)
@@ -132,6 +132,12 @@
 	PARSEELF = -e
 endif
 
+ifeq ($(CONFIG_WHOLE_PROGRAM_COMPILE), y)
+	COMBINEFLAGS = -fwhole-program
+else
+	COMBINEFLAGS =
+endif
+
 STAGE0_SRC := $(patsubst %,$(src)/lib/%,$(STAGE0_LIB_SRC)) \
 	      $(patsubst %,$(src)/arch/x86/%,$(STAGE0_ARCH_X86_SRC)) \
 	      $(STAGE0_MAINBOARD_SRC) $(STAGE0_CHIPSET_SRC)
@@ -268,7 +274,7 @@
 
 $(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
-	$(Q)$(CC) $(INITCFLAGS) -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
+	$(Q)$(CC) $(INITCFLAGS) -fPIE -c -combine $(COMBINEFLAGS) $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
 
 	$(Q)# .data and .bss must be empty because they aren't handled
 	$(Q)printf "  CHECK   initram (non-empty writable/allocatable sections)\n"





More information about the coreboot mailing list