[coreboot] r812 - coreboot-v3/arch/x86/amd

[svn at coreboot.org]

Author: rminnich
Date: 2008-08-24 09:08:17 +0200 (Sun, 24 Aug 2008)
New Revision: 812

Modified:
   coreboot-v3/arch/x86/amd/stage0.S
Log:
It's a good idea to set up the segment registers.

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/arch/x86/amd/stage0.S
===================================================================
--- coreboot-v3/arch/x86/amd/stage0.S	2008-08-24 06:16:03 UTC (rev 811)
+++ coreboot-v3/arch/x86/amd/stage0.S	2008-08-24 07:08:17 UTC (rev 812)
@@ -163,6 +163,21 @@
 	/* Save the BIST result */
 	movl	%eax, %ebp
 
+	/* Save the BIST value. */
+	movl	%eax, %ebp
+
+	port80_post(0x01)
+
+	movw	$ROM_DATA_SEG, %ax
+	movw	%ax, %ds
+	movw	%ax, %es
+	movw	%ax, %ss
+	movw	%ax, %fs
+	movw	%ax, %gs
+
+	/* Restore the BIST value to %eax. */
+	movl	%ebp, %eax
+
 	/*for normal part %ebx already contain cpu_init_detected from fallback call */
 
 cache_as_ram_setup: