[coreboot] [PATCH] artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size)

Mart Raudsepp mart.raudsepp at artecdesign.ee
Wed Aug 13 19:37:01 CEST 2008

Ühel kenal päeval, T, 2008-08-12 kell 20:02, kirjutas ron minnich:
> If you have more than one dbe62 board working with this setting,

I ran memtest again for 1h40min on the same board, doing a full pass and
a half, and also on another DBE62 board for 52 minutes doing one full
pass exactly.

> So, if you can do an svn diff, make sure this is all that's really
> different, and it works on your hardware, this is

That was the only difference that made it work, yes. The 1h40 and 52min
tests were made with trunk + just this change.

> Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Thanks, committed as r757 together with Carl-Daniels ack.

Next I want to work a bit on clarifying some of these fake SPD things in
comments, perhaps improving some related debug printing code, and
getting the DBE61 to work that I have at home (not sure which memory
configuration it was).
I should also clean up and post to util/ my lxmemregs tool that quickly
tells me what a memory related register value actually means, by
converting a given hex of MC_CF8F_DATA or MC_CF1017_DATA to readable
text, a la

tRFC: <value>
tRC: <value>

Maybe there is already a similar more generic tool for any register that
these memory registers can be added onto if necessary? I vaguely recall
something that used a special registry description file to describe
things in a generic way?

With Regards,
Mart Raudsepp
Artec Design LLC

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