[coreboot] r757 - coreboot-v3/mainboard/artecgroup/dbe62

svn at coreboot.org svn at coreboot.org
Wed Aug 13 19:21:10 CEST 2008

Author: mraudsepp
Date: 2008-08-13 19:21:09 +0200 (Wed, 13 Aug 2008)
New Revision: 757

artecgroup/dbe62: Fix SPD_NUM_COLUMNS value (DIMM page size)

This changes SPD_NUM_COLUMNS from 0x8 back to 0xa, as it was originally when
copied over from another board, because 0x8 evaluates to 2kB, not 8kB, while 0xa
does the latter. 8kB is what the chip has and what is also set in our currently
used firmwares for DBE62.

This (combined with all the previous committed hard work from Ron before) fixes
memtest86+ freezes and hard reboots for me in quick 30 minute testing time,
while before it would freeze or reboot just into 50% of first test.

There is more to do to get the optimum RAM setup, but this should do for now -
the rest is just optimizing to quicker timings, while current ones in the fake
SPD are very conservative.

Signed-off-by: Mart Raudsepp <mart.raudsepp at artecdesign.ee>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
Acked-by: Ronald G. Minnich <rminnich at gmail.com>

Modified: coreboot-v3/mainboard/artecgroup/dbe62/initram.c
--- coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-08-13 15:41:04 UTC (rev 756)
+++ coreboot-v3/mainboard/artecgroup/dbe62/initram.c	2008-08-13 17:21:09 UTC (rev 757)
@@ -65,7 +65,7 @@
 	{SPD_tRP, 0x58},
+	{SPD_NUM_COLUMNS, 0xa}, /* 8kB */
 	{SPD_REFRESH, 0x82},

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