[coreboot] r752 - in coreboot-v3: arch/x86 include/device

[svn at coreboot.org]

Author: rminnich
Date: 2008-08-13 04:41:29 +0200 (Wed, 13 Aug 2008)
New Revision: 752

Modified:
   coreboot-v3/arch/x86/pci_ops_auto.c
   coreboot-v3/arch/x86/pci_ops_conf1.c
   coreboot-v3/include/device/pci_ops.h
Log:
Here we start to see the good design of 3. In v2, there were pci ops in 
all stages, blighting everything with the same code, compiled different 
ways. In this change, we see that:
- basic conf ops are compiled into stage0, where they are used. 
- they are called directly from initram
- they are used to initialize the pci_cf8_conf1 structure in stage 2, 
   but the call still goes to stage0!

one copy of the code. 

Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>


Modified: coreboot-v3/arch/x86/pci_ops_auto.c
===================================================================
--- coreboot-v3/arch/x86/pci_ops_auto.c	2008-08-12 23:54:25 UTC (rev 751)
+++ coreboot-v3/arch/x86/pci_ops_auto.c	2008-08-13 02:41:29 UTC (rev 752)
@@ -7,6 +7,18 @@
 #include <types.h>
 #include <io.h>
 
+
+const struct pci_bus_operations pci_cf8_conf1 = {
+	.read8  = pci_conf1_read_config8,
+	.read16 = pci_conf1_read_config16,
+	.read32 = pci_conf1_read_config32,
+	.write8  = pci_conf1_write_config8,
+	.write16 = pci_conf1_write_config16,
+	.write32 = pci_conf1_write_config32,
+	.find = 	pci_conf1_find_device,
+};
+
+
 /*
  * Before we decide to use direct hardware access mechanisms, we try to do some
  * trivial checks to ensure it at least _seems_ to be working -- we just test

Modified: coreboot-v3/arch/x86/pci_ops_conf1.c
===================================================================
--- coreboot-v3/arch/x86/pci_ops_conf1.c	2008-08-12 23:54:25 UTC (rev 751)
+++ coreboot-v3/arch/x86/pci_ops_conf1.c	2008-08-13 02:41:29 UTC (rev 752)
@@ -56,37 +56,37 @@
 #define CONFIG_CMD(bdf, where)   (0x80000000 | (bdf) | ((where & 0xff) & ~3) | ((where & 0xf00)<<16) )
 #endif
 
-static u8 pci_conf1_read_config8(u32 bdf, int where)
+u8 pci_conf1_read_config8(u32 bdf, int where)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		return inb(0xCFC + (where & 3));
 }
 
-static u16 pci_conf1_read_config16(u32 bdf, int where)
+u16 pci_conf1_read_config16(u32 bdf, int where)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		return inw(0xCFC + (where & 2));
 }
 
-static u32 pci_conf1_read_config32(u32 bdf, int where)
+u32 pci_conf1_read_config32(u32 bdf, int where)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		return inl(0xCFC);
 }
 
-static void  pci_conf1_write_config8(u32 bdf, int where, u8 value)
+void  pci_conf1_write_config8(u32 bdf, int where, u8 value)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		outb(value, 0xCFC + (where & 3));
 }
 
-static void pci_conf1_write_config16(u32 bdf, int where, u16 value)
+void pci_conf1_write_config16(u32 bdf, int where, u16 value)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		outw(value, 0xCFC + (where & 2));
 }
 
-static void pci_conf1_write_config32(u32 bdf, int where, u32 value)
+void pci_conf1_write_config32(u32 bdf, int where, u32 value)
 {
 		outl(CONFIG_CMD(bdf, where), 0xCF8);
 		outl(value, 0xCFC);
@@ -111,7 +111,7 @@
  * @return 1 if found, 0 otherwise
  */
 
-static int find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn)
+int pci_conf1_find_on_bus(u16 bus, u16 vid, u16 did, u32 *busdevfn)
 
 {
 	u16 devfn;
@@ -139,7 +139,7 @@
 		if (hdr == PCI_HEADER_TYPE_BRIDGE || hdr == PCI_HEADER_TYPE_CARDBUS) {
 			unsigned int busses;
 			busses = pci_conf1_read_config32(confaddr, PCI_PRIMARY_BUS);
-			if (find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn))
+			if (pci_conf1_find_on_bus((busses >> 8) & 0xFF, vid, did, busdevfn))
 				return 1;
 		}
 	}
@@ -147,17 +147,7 @@
 	return 0;
 }
 
-static int pci_find_device(u16 vid, u16 did, u32 * dev)
+int pci_conf1_find_device(u16 vid, u16 did, u32 * dev)
 {
-	return find_on_bus(0, vid, did, dev);
+	return pci_conf1_find_on_bus(0, vid, did, dev);
 }
-
-const struct pci_bus_operations pci_cf8_conf1 = {
-	.read8  = pci_conf1_read_config8,
-	.read16 = pci_conf1_read_config16,
-	.read32 = pci_conf1_read_config32,
-	.write8  = pci_conf1_write_config8,
-	.write16 = pci_conf1_write_config16,
-	.write32 = pci_conf1_write_config32,
-	.find = 	pci_find_device,
-};

Modified: coreboot-v3/include/device/pci_ops.h
===================================================================
--- coreboot-v3/include/device/pci_ops.h	2008-08-12 23:54:25 UTC (rev 751)
+++ coreboot-v3/include/device/pci_ops.h	2008-08-13 02:41:29 UTC (rev 752)
@@ -21,6 +21,7 @@
 #include <types.h>
 #include <device/device.h>
 #include <pci_ops.h>
+#include <shared.h>
 
 u8 pci_read_config8(struct device * dev, unsigned where);
 u16 pci_read_config16(struct device * dev, unsigned where);
@@ -29,4 +30,13 @@
 void pci_write_config16(struct device * dev, unsigned where, u16 val);
 void pci_write_config32(struct device * dev, unsigned where, u32 val);
 
+SHARED(pci_conf1_read_config8, u8, u32 bdf, int where);
+SHARED(pci_conf1_read_config16, u16, u32 bdf, int where);
+SHARED(pci_conf1_read_config32, u32, u32 bdf, int where);
+SHARED(pci_conf1_write_config8, void , u32 bdf, int where, u8 value);
+SHARED(pci_conf1_write_config16, void, u32 bdf, int where, u16 value);
+SHARED(pci_conf1_write_config32, void, u32 bdf, int where, u32 value);
+SHARED(pci_conf1_find_on_bus, int, u16 bus, u16 vid, u16 did, u32 *busdevfn);
+SHARED(pci_conf1_find_device, int, u16 vid, u16 did, u32 * dev);
+
 #endif /* DEVICE_PCI_OPS_H */