[coreboot] patch: mcp55 sata

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Mon Aug 11 12:28:48 CEST 2008


On 11.08.2008 07:46, ron minnich wrote:
> compiles and dts works.
>
> ron
>
>
> Add mcp55 sata support. 
>
> This compiles and the dts works as well. 
>
> Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
>   

With the comments addressed:
Acked-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Regards,
Carl-Daniel
> Index: southbridge/nvidia/mcp55/sata.c
> ===================================================================
> --- southbridge/nvidia/mcp55/sata.c	(revision 0)
> +++ southbridge/nvidia/mcp55/sata.c	(revision 0)
> @@ -0,0 +1,92 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2004 Tyan Computer
> + * Written by Yinghai Lu <yhlu at tyan.com> for Tyan Computer.
> + * Copyright (C) 2006,2007 AMD
> + * Written by Yinghai Lu <yinghai.lu at amd.com> for AMD.
> + *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +#include <types.h>
> +#include <lib.h>
> +#include <console.h>
> +#include <device/pci.h>
> +#include <msr.h>
> +#include <legacy.h>
> +#include <device/pci_ids.h>
> +#include <statictree.h>
> +#include <config.h>
> +#include "mcp55.h"
> +
> +
> +static void sata_init(struct device *dev)
> +{
> +	u32 dword;
> +
> +	struct southbridge_nvidia_mcp55_sata_config *conf =
> +	    (struct southbridge_nvidia_mcp55_sata_config *)dev->device_configuration;
> +
> +	dword = pci_read_config32(dev, 0x50);
> +	/* Ensure prefetch is disabled */
> +	dword &= ~((1 << 15) | (1 << 13));
> +	if(conf) {
> +		if (conf->sata1_enable) {
> +			/* Enable secondary SATA interface */
> +			dword |= (1<<0);
> +			printk(BIOS_DEBUG, "SATA S \t");
>   

Move the comment into the printk, please.

> +		}
> +		if (conf->sata0_enable) {
> +			/* Enable primary SATA interface */
> +			dword |= (1<<1);
> +			printk(BIOS_DEBUG, "SATA P \n");
>   

Same here.

> +		}
> +	} else {
> +		dword |= (1<<1) | (1<<0);
> +		printk(BIOS_DEBUG, "SATA P and S \n");
>   

printk with a similar text as mentioned above.

> +	}
> +
> +
> +#if 1
>   

Superfluous #if 1

> +	dword &= ~(0x1f<<24);
> +	dword |= (0x15<<24);
> +#endif
> +	pci_write_config32(dev, 0x50, dword);
> +
> +	dword = pci_read_config32(dev, 0xf8);
> +	dword |= 2;
> +	pci_write_config32(dev, 0xf8, dword);
> +
> +
> +#warning finish set subsystem in mcp55 sata
> +#if 0
>   

As commented in another review: Separate function please.

> +	pci_write_config32(dev, 0x40,
> +		((device & 0xffff) << 16) | (vendor & 0xffff));
> +#endif
> +}
> +
> +struct device_operations mcp55_ide = {
> +	.id = {.type = DEVICE_ID_PCI,
> +		{.pci = {.vendor = PCI_VENDOR_ID_NVIDIA,
> +			      .device = PCI_DEVICE_ID_NVIDIA_MCP55_SATA1}}},
> +	.constructor		 = default_device_constructor,
> +	.phase3_scan		 = 0,
> +	.phase4_read_resources	 = pci_dev_read_resources,
> +	.phase4_set_resources	 = pci_dev_set_resources,
> +	.phase5_enable_resources = pci_dev_enable_resources,
> +	.phase6_init		 = sata_init,
> +	.ops_pci		 = &pci_dev_ops_pci,
> +};
> Index: southbridge/nvidia/mcp55/sata.dts
> ===================================================================
> --- southbridge/nvidia/mcp55/sata.dts	(revision 0)
> +++ southbridge/nvidia/mcp55/sata.dts	(revision 0)
> @@ -0,0 +1,26 @@
> +/*
> + * This file is part of the coreboot project.
> + *
> + * Copyright (C) 2007-8 Ronald G. Minnich <rminnich at gmail.com> *
> + * This program is free software; you can redistribute it and/or modify
> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation; either version 2 of the License, or
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY; without even the implied warranty of
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program; if not, write to the Free Software
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +{
> +	device_operations = "mcp55_sata";
> +
> +	sata0_enable = "0";
> +	sata1_enable = "0";
> +
> +};
>   

-- 
http://www.hailfinger.org/





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