[coreboot] [PATCH] v3: convert stage2 and initram makefile rules from object to source files

Carl-Daniel Hailfinger c-d.hailfinger.devel.2006 at gmx.net
Sat Aug 2 20:47:58 CEST 2008


On 01.03.2008 20:26, Carl-Daniel Hailfinger wrote:
> Convert stage2 and initram makefile rules from object to source files. 
> This creates a clearer distinction between source files in the source 
> tree we want to have compiled and indirectly created object/source files 
> in the object tree.
>
> It also will make enable us to move to whole-program 
> optimization/compilation which should yield substantial size savings.
> Then again, we may be able to do that without the makefile conversion as 
> well.
>
> Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
>   

Updated patch for svn HEAD follows.

Index: corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/amd/cs5536/Makefile	(Arbeitskopie)
@@ -21,7 +21,7 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_AMD_CS5536),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/cs5536.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/amd/cs5536/cs5536.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
 STAGE2_CHIPSET_OBJ += $(obj)/southbridge/amd/cs5536/irq_tables.o 
Index: corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile
===================================================================
--- corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/southbridge/intel/i82371eb/Makefile	(Arbeitskopie)
@@ -20,6 +20,6 @@
 
 ifeq ($(CONFIG_SOUTHBRIDGE_INTEL_I82371EB),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/southbridge/intel/i82371eb/i82371eb.o
+STAGE2_CHIPSET_SRC += $(src)/southbridge/intel/i82371eb/i82371eb.c
 
 endif
Index: corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/winbond/w83627hf/Makefile	(Arbeitskopie)
@@ -25,6 +25,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/winbond/w83627hf/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/winbond/w83627hf/superio.c
 
 endif
Index: corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile
===================================================================
--- corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/superio/fintek/f71805f/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 STAGE0_CHIPSET_OBJ += $(obj)/device/pnp_raw.o
 
 # Always add to variables, as there could be more than one Super I/O.
-STAGE2_CHIPSET_OBJ += $(obj)/superio/fintek/f71805f/superio.o
+STAGE2_CHIPSET_SRC += $(src)/superio/fintek/f71805f/superio.c
 
 endif
Index: corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/adl/msm800sev/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ =
+STAGE2_MAINBOARD_SRC =
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/amd/norwich/Makefile	(Arbeitskopie)
@@ -21,12 +21,12 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/southbridge/amd/cs5536/smbus_initram.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe61/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/artecgroup/dbe62/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c $(src)/lib/ramtest.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/pcengines/alix1c/Makefile	(Arbeitskopie)
@@ -21,11 +21,11 @@
 
 STAGE0_MAINBOARD_OBJ := $(obj)/mainboard/$(MAINBOARDDIR)/stage1.o
 
-INITRAM_OBJ =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC =   $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/northbridge/amd/geodelx/raminit.c \
 		$(src)/arch/x86/geodelx/geodelx.c
 
-STAGE2_MAINBOARD_OBJ = 
+STAGE2_MAINBOARD_SRC = 
 
 $(obj)/coreboot.vpd:
 	$(Q)printf "  BUILD   DUMMY VPD\n"
Index: corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/mainboard/emulation/qemu-x86/Makefile	(Arbeitskopie)
@@ -28,10 +28,10 @@
 # directory and is built from what was auto.c in v2.
 #
 
-INITRAM_OBJ = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
+INITRAM_SRC = $(src)/mainboard/$(MAINBOARDDIR)/initram.c \
 		$(src)/mainboard/$(MAINBOARDDIR)/initram_printktest.c
 
-STAGE2_MAINBOARD_OBJ = vga.o
+STAGE2_MAINBOARD_SRC = vga.c
 
 #
 # VPD or SIP ROM or... how does NVIDIA call it?
Index: corebootv3-makefilerewrite/device/Makefile
===================================================================
--- corebootv3-makefilerewrite/device/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/device/Makefile	(Arbeitskopie)
@@ -24,6 +24,6 @@
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(CC) $(INITCFLAGS) -c $< -o $@
 
-STAGE2_DEVICE_OBJ = device.o device_util.o root_device.o \
-		    pci_device.o pci_ops.o pci_rom.o pnp_device.o pnp_raw.o
+STAGE2_DEVICE_SRC = device.c device_util.c root_device.c \
+		    pci_device.c pci_ops.c pci_rom.c pnp_device.c pnp_raw.c
 
Index: corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/amd/geodelx/Makefile	(Arbeitskopie)
@@ -21,9 +21,9 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_AMD_GEODELX),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/amd/geodelx/geodelx.o \
-		      $(obj)/northbridge/amd/geodelx/vsmsetup.o \
-		      $(obj)/util/x86emu/vm86_gdt.o \
-		      $(obj)/northbridge/amd/geodelx/grphinit.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/amd/geodelx/geodelx.c \
+		      $(src)/northbridge/amd/geodelx/vsmsetup.c \
+		      $(src)/util/x86emu/vm86_gdt.c \
+		      $(src)/northbridge/amd/geodelx/grphinit.c
 
 endif
Index: corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile
===================================================================
--- corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/northbridge/intel/i440bxemulation/Makefile	(Arbeitskopie)
@@ -21,6 +21,6 @@
 
 ifeq ($(CONFIG_NORTHBRIDGE_INTEL_I440BXEMULATION),y)
 
-STAGE2_CHIPSET_OBJ += $(obj)/northbridge/intel/i440bxemulation/i440bx.o
+STAGE2_CHIPSET_SRC += $(src)/northbridge/intel/i440bxemulation/i440bx.c
 
 endif
Index: corebootv3-makefilerewrite/arch/x86/Makefile
===================================================================
--- corebootv3-makefilerewrite/arch/x86/Makefile	(Revision 713)
+++ corebootv3-makefilerewrite/arch/x86/Makefile	(Arbeitskopie)
@@ -178,27 +178,32 @@
 # TODO: This should be compressed with the default compressor.
 #
 
-STAGE2_LIB_OBJ       = stage2.o clog2.o mem.o tables.o delay.o \
-		       compute_ip_checksum.o string.o
+STAGE2_LIB_SRC       = stage2.c clog2.c mem.c tables.c delay.c \
+		       compute_ip_checksum.c string.c
 
-STAGE2_ARCH_X86_OBJ  = archtables.o coreboot_table.o udelay_io.o
-STAGE2_ARCH_X86_OBJ += pci_ops_auto.o pci_ops_conf1.o pci_ops_conf2.o
-STAGE2_ARCH_X86_OBJ += keyboard.o i8259.o isa-dma.o
+STAGE2_ARCH_X86_SRC  = archtables.c coreboot_table.c udelay_io.c
+STAGE2_ARCH_X86_SRC += pci_ops_auto.c pci_ops_conf1.c pci_ops_conf2.c
+STAGE2_ARCH_X86_SRC += keyboard.c i8259.c isa-dma.c
 
 ifeq ($(CONFIG_PIRQ_TABLE),y)
-STAGE2_ARCH_X86_OBJ += pirq_routing.o
+STAGE2_ARCH_X86_SRC += pirq_routing.c
 endif
 
 STAGE2_DYNAMIC_OBJ   = statictree.o
 
-STAGE2_OBJ := $(patsubst %,$(obj)/lib/%,$(STAGE2_LIB_OBJ)) \
-	      $(patsubst %,$(obj)/arch/x86/%,$(STAGE2_ARCH_X86_OBJ)) \
-	      $(patsubst %,$(obj)/device/%,$(STAGE2_DEVICE_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_OBJ)) \
-	      $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+STAGE2_SRC := $(patsubst %,$(src)/lib/%,$(STAGE2_LIB_SRC)) \
+	      $(patsubst %,$(src)/arch/x86/%,$(STAGE2_ARCH_X86_SRC)) \
+	      $(patsubst %,$(src)/device/%,$(STAGE2_DEVICE_SRC)) \
+	      $(patsubst %,$(src)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_MAINBOARD_SRC))
 
-STAGE2_OBJ += $(STAGE2_CHIPSET_OBJ)
+STAGE2_SRC += $(STAGE2_CHIPSET_SRC)
 
+STAGE2_OBJ := $(patsubst $(src)/%.c,$(obj)/%.o,$(STAGE2_SRC))
+
+# This one is special, but only due to slightly incorrect rules and dependencies.
+# Don't change the dependencies for now.
+STAGE2_OBJ += $(patsubst %,$(obj)/mainboard/$(MAINBOARDDIR)/%,$(STAGE2_DYNAMIC_OBJ))
+
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN),y)
 ifeq ($(CONFIG_PCI_OPTION_ROM_RUN_X86EMU),y)
 # x86emu wants libgcc
@@ -214,7 +219,7 @@
 
 STAGE2_OBJ_NEEDED = $(filter-out $(STAGE0_OBJ), $(STAGE2_OBJ))
 
-$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED)
+$(obj)/coreboot.stage2 $(obj)/coreboot.stage2.map: $(obj)/stage0.o $(STAGE2_OBJ_NEEDED) $(STAGE2_SRC)
 	$(Q)# leave a .o with full symbols in it for debugging.
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -R $(obj)/stage0.o -Ttext 0x2000 --entry=stage2 \
@@ -260,9 +265,9 @@
 	$(Q)printf "  AS      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(AS) $(obj)/arch/x86/stage0_asm.s -o $@
 
-$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_OBJ)
+$(obj)/coreboot.initram $(obj)/coreboot.initram.map: $(obj)/stage0.init $(obj)/stage0-prefixed.o $(INITRAM_SRC)
 	$(Q)printf "  CC      $(subst $(shell pwd)/,,$(@)) (XIP)\n"
-	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_OBJ) -o $(obj)/coreboot.initram_partiallylinked.o
+	$(Q)$(CC) $(INITCFLAGS) -D_SHARED -fPIE -c -combine $(INITRAM_SRC) -o $(obj)/coreboot.initram_partiallylinked.o
 	$(Q)# initram links against stage0
 	$(Q)printf "  LD      $(subst $(shell pwd)/,,$(@))\n"
 	$(Q)$(LD) -Ttext 0 --entry main -N -R $(obj)/stage0-prefixed.o \



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