[coreboot] r671 - coreboot-v3/northbridge/amd/geodelx

[svn at coreboot.org]

Author: rminnich
Date: 2008-04-30 06:12:56 +0200 (Wed, 30 Apr 2008)
New Revision: 671

Modified:
   coreboot-v3/northbridge/amd/geodelx/raminit.c
Log:
Rework Geode LX RAMinit DIMM size formula to be more
understandable. Added benefit is complaining loudly for
unsupported 2 GB DIMM size.

Signed-off-by: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>

Tested on the dbe62 up to and including Etherboot. 

Acked-by: Ronald G. Minnich <rminnich at gmail.com>



Modified: coreboot-v3/northbridge/amd/geodelx/raminit.c
===================================================================
--- coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-04-29 11:49:42 UTC (rev 670)
+++ coreboot-v3/northbridge/amd/geodelx/raminit.c	2008-04-30 04:12:56 UTC (rev 671)
@@ -151,16 +151,12 @@
 	banner(BIOS_DEBUG, "SPDBANKDENSITY");
 	dimm_size = spd_read_byte(dimm, SPD_BANK_DENSITY);
 
-	/* Align so 1 GB (bit 0) is bit 8. This is a little weird to get gcc
-	 * to not optimize this out.
-	 */
-	dimm_size |= (dimm_size << 8);
+       /* Bits 0-1 have been redefined by JEDEC to contain what would have
+        * been in non-existing bits 8 (1GB) and 9 (2GB). Move bits 0-1 to
+        * bits 8-9 and mask bits 0-1 off.
+        */
+	dimm_size = ((dimm_size & 0x3) << 8) | (dimm_size & ~0x3);
 
-	/* And off 2 GB DIMM size: not supported and the 1 GB size we just
-	 * moved up to bit 8 as well as all the extra on top.
-	 */
-	dimm_size &= 0x01FC;
-
 	/* Module Density * Module Banks */
 	/* Shift to multiply by the number of DIMM banks. */
 	dimm_size <<= (dimm_setting >> CF07_UPPER_D0_MB_SHIFT) & 1;