[coreboot] Fwd: DBE62 v3 strangeness since v3 rev 649
Marc.Jones at amd.com
Tue Apr 29 17:44:54 CEST 2008
ron minnich wrote:
> If somebody could ack this I can close out the recent dbe62 problems.
Acked-by: Marc Jones <marc.jones at amd.com>
> ---------- Forwarded message ----------
> From: ron minnich <rminnich at gmail.com>
> Date: Fri, Apr 18, 2008 at 10:09 PM
> Subject: Re: DBE62 v3 strangeness since v3 rev 649
> To: Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>
> Cc: Coreboot <coreboot at coreboot.org>
> On Tue, Apr 15, 2008 at 2:52 PM, Carl-Daniel Hailfinger
> <c-d.hailfinger.devel.2006 at gmx.net> wrote:
>> Hi Ron,
> > this one is for you: Your commit 649 had a few probably unintended side
> > effects:
> > - set_delay_control thinks zero DIMMs are installed because
> > SPD_PRIMARY_SDRAM_WIDTH does not exist in the SPD table.
> > - Due to that, the GLCP_DELAY_CONTROLS msr is set to 0.
> > Please confirm that you really wanted these settings.
> This mistake arose out of my attempt to clean up the namings of things
> in the original initram. It had names from two sources.
> This patch cleans up that error, and is my attempt at cleaning up the
> null pointer
> issue in device/device.c, which I actually don't understand.
> This patch allows me to almost boot a Plan 9 kernel from flash.
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
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