[coreboot] r3253 - in trunk/coreboot-v2/src: mainboard/tyan/s2891 southbridge/nvidia/ck804

[svn at coreboot.org]

Author: ward
Date: 2008-04-23 02:40:39 +0200 (Wed, 23 Apr 2008)
New Revision: 3253

Modified:
   trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c
   trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
Log:

This patch fixes the 3 broken sata ports on the Tyan s2891 (primary port on
secondary controller was ok). There were two problems: the master sata
controller was not being initialized, and the irqs for the secondary ports on
both controllers were not being set in the mptable.

Thanks for Jonathan Kollasch for all the help figuring out the IRQ problem.

While all ports work reliably under a recent kernel (2.6.24), sata is about
half as fast as under the proprietary bios, according to bonnie++. That still
needs fixing...

Signed-off-by: Ward Vandewege <ward at gnu.org>
Acked-by: Myles Watson <mylesgw at gmail.com>



Modified: trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c
===================================================================
--- trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c	2008-04-22 23:32:56 UTC (rev 3252)
+++ trunk/coreboot-v2/src/mainboard/tyan/s2891/mptable.c	2008-04-23 00:40:39 UTC (rev 3253)
@@ -79,7 +79,7 @@
         
 	/* Initialize interrupt mapping*/
 
-			dword = 0x0000d218;
+			dword = 0x0120d218;
 	        	pci_write_config32(dev, 0x7c, dword);
 
 		        dword = 0x12008a00;

Modified: trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c
===================================================================
--- trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-04-22 23:32:56 UTC (rev 3252)
+++ trunk/coreboot-v2/src/southbridge/nvidia/ck804/ck804_early_setup.c	2008-04-23 00:40:39 UTC (rev 3253)
@@ -228,6 +228,18 @@
         RES_PORT_IO_32, CK804B_ANACTRL_IO_BASE + 0x24, 0xfcffff0f, 0x020000b0,
 #endif
 
+    // Activate master port on primary SATA controller
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x50), ~(0x1f000013), 0x15000013,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x64), ~(0x00000001), 0x00000001,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x68), ~(0x02000000), 0x02000000,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x70), ~(0x000f0000), 0x00040000,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xa0), ~(0x000001ff), 0x00000150,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xac), ~(0xffff8f00), 0x02aa8b00,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0x7c), ~(0x00000010), 0x00000000,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xc8), ~(0x0fff0fff), 0x000a000a,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xd0), ~(0xf0000000), 0x00000000,
+    RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+7 , 0, 0xe0), ~(0xf0000000), 0x00000000,
+	
     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x50), ~(0x1f000013), 0x15000013,
     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x64), ~(0x00000001), 0x00000001,
     RES_PCI_IO, PCI_ADDR(0, CK804_DEVN_BASE+8 , 0, 0x68), ~(0x02000000), 0x02000000,