[coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset

Jeremy Jackson jerj at coplanar.net
Wed Apr 16 18:40:34 CEST 2008

On Wed, 2008-04-16 at 18:12 +0200, Carl-Daniel Hailfinger wrote:

> > What is the longest amount of time between any two POST code updates?
> > The only think I can think of is ECC ram clearing.
> >   
> One hour, probably longer. A payload is not guaranteed to poke the TCO
> timer, so as long as the payload is running, the TCO timer could fire in
> theory.

This is another feature to add to the list of payload flags.

assumes payload is specific to the board's TCO timer, 

or just disable it for the *payload*... still useful for normal/fallback

Jeremy Jackson
Coplanar Networks
jerj at coplanar.net

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