[coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset

Jeremy Jackson jerj at coplanar.net
Wed Apr 16 17:55:09 CEST 2008

On Wed, 2008-04-16 at 17:33 +0200, Carl-Daniel Hailfinger wrote:

> Please avoid any POST code toggling. There are POST boards out there
> which display the last n POST codes and make it a lot easier to follow
> the code path. Once you add POST code toggling, that history is flushed
> away really fast.

Perhaps a config option?   The same function/inline/macro could be put
in the code, but de-toothed as far as toggling, for those with a fancier
POST card.

Toggling aside, the original idea was, to point out there is one thing
which pokes "keepalive" info already, and perhaps it's just a matter of
directing that poke to include the TCO timer.

What is the longest amount of time between any two POST code updates?
The only think I can think of is ECC ram clearing.

Jeremy Jackson
Coplanar Networks
jerj at coplanar.net

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