[coreboot] DBE62 v3 strangeness since v3 rev 649

[Carl-Daniel Hailfinger]

Hi Ron,

this one is for you: Your commit 649 had a few probably unintended side
effects:
- set_delay_control thinks zero DIMMs are installed because
SPD_PRIMARY_SDRAM_WIDTH does not exist in the SPD table.
- Due to that, the GLCP_DELAY_CONTROLS msr is set to 0.

Please confirm that you really wanted these settings.

Regards,
Carl-Daniel