[coreboot] [patch][v2] AMD Fam10 memory controller updates
Marc Jones
Marc.Jones at amd.com
Wed Apr 9 00:28:02 CEST 2008
Peter Stuge wrote:
> On Tue, Apr 08, 2008 at 09:27:15AM -0600, Marc Jones wrote:
>
>> Removed confusing whitespace changes.
>>
>
> Awesome. Made the patch 1/3 smaller too!
>
>
> Two questions:
>
>
>> Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mct_d.c
>> @@ -3358,10 +3395,8 @@
>> /* Tri-state unused ODTs when motherboard termination is available */
>>
>> // FIXME: skip for Ax
>> -
>> - dev = pDCTstat->dev_dct;
>> - word = 0;
>> - for (cs = 0; cs < 8; cs += 2) {
>> + // FIXME: BUG53109 function can incorrectly program F2x[1,0]9C_x0C[11:8]_ODTTri
>> +/* for (cs = 0; cs < 8; cs += 2) {
>> if (!(pDCTstat->CSPresent & (1 << cs))) {
>> if (!(pDCTstat->CSPresent & (1 << (cs + 1))))
>> word |= (1 << (cs >> 1));
>> @@ -3372,6 +3407,7 @@
>> val = Get_NB32_index_wait(dev, index_reg, index);
>> val |= (word << 8);
>> Set_NB32_index_wait(dev, index_reg, index, val);
>> +*/
>> }
>>
>
> Can you comment on this comment? Why not just remove the code?
>
>
>
The code was close to what needed to be done but some final details
needed to be worked out by some people that know better than me. Turns
out they have made the changes so I have added the fix back in.
>> Index: coreboot-v2/src/northbridge/amd/amdmct/mct/mctecc_d.c
>> @@ -101,7 +101,7 @@
>>
>> OF_ScrubCTL = 0; /* Scrub CTL for Dcache, L2, and dram */
>> val = mctGet_NVbits(NV_DCBKScrub);
>> - mct_AdjustScrub_D(pDCTstatA, val);
>> + mct_AdjustScrub_D(pDCTstatA, (u16) &val);
>>
>
> Will this really work?
>
> val is u32, mct_AdjustScrub_D() wants u16*, isn't this
> casting/truncating the pointer?
>
>
This was a good catch. I decided to add a nvbits variable. Reusing val
was not really needed. That is just the register constrained asm
programmer in me.
New patch attached.
Marc
--
Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com
http://www.amd.com/embeddedprocessors
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