[coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset

joe at smittys.pointclark.net joe at smittys.pointclark.net
Thu Apr 3 18:34:04 CEST 2008

Quoting Ed Swierk <eswierk at arastra.com>:

> On Wed, Apr 2, 2008 at 10:48 AM,  <joe at smittys.pointclark.net> wrote:
>>  Hmm, this is going to be interesting on the ICH4, I still have to look at
>> how the other ICH's are setup. The TCO Timer Halt is acually located in I/O
>> space not PCI configuration space. It is ACPIBASE + TCOBASE(60h) +
>> TCO1_CNT(08h) bit 11. We'll see.
> This is exactly how it works on the Intel 3100; see
> i3100_halt_tco_timer() in my patch
> (http://qa.coreboot.org/log_commit.php?revision=3198).
> --Ed
Wow your right:-) Looks like the only difference is the I/O Base  
address is 0x00000500 on the ICH series, this should be simple than.  
Thanks for laying down the base code Ed :-)

Thanks - Joe

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