[coreboot] [PATCH] Halt TCO timer on Intel 3100 chipset

joe at smittys.pointclark.net joe at smittys.pointclark.net
Wed Apr 2 19:48:37 CEST 2008

Quoting Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net>:

> On 30.03.2008 16:18, joe at smittys.pointclark.net wrote:
>> Quoting Ed Swierk <eswierk at arastra.com>:
>>> On Sat, Mar 29, 2008 at 5:20 PM,  <joe at smittys.pointclark.net> wrote:
>>>> After thinking about it.....
>>>> What are the advantages of disabling the TCO timer (besides
>>>> rebooting)? Doesn't the system need this to run properly? By setting
>>>> the no reboot the timer is still running....does it need to be?
>>> The point of the TCO timer is to let a system recover automatically by
>>> sending an interrupt and then rebooting if the OS crashes. While
>>> operating systems can crash for all sorts of reasons, coreboot code
>>> doesn't generally crash unless there's a hardware failure or
>>> misconfiguration that will not correct itself by rebooting. Thus it
>>> makes sense to disable the timer in coreboot and let a TCO-aware
>>> payload re-enable it.
>>> The TCO timer has no other purpose that I'm aware of, so it doesn't
>>> matter whether coreboot neuters its effect by setting NO_REBOOT or
>>> halts it completely by setting TCO_TMR_HALT. Leaving the timer running
>>> still causes an interrupt to occur on timeout, but I think it's a
>>> no-op unless the OS is paying attention.
>>> This document explains the TCO timer in more detail:
>>> ftp://download.intel.com/design/chipsets/applnots/29227301.pdf.
>> Thanks for the explanation Ed. That makes perfect sense.
> Please halt the timer completely if possible. We are not really prepared
> to handle interrupts in coreboot.
Hmm, this is going to be interesting on the ICH4, I still have to look  
at how the other ICH's are setup. The TCO Timer Halt is acually  
located in I/O space not PCI configuration space. It is ACPIBASE +  
TCOBASE(60h) + TCO1_CNT(08h) bit 11. We'll see.

Thanks - Joe

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