[LinuxBIOS] WIP Support for RCA RM4100 - i82830 Complete

joe at smittys.pointclark.net joe at smittys.pointclark.net
Tue Sep 18 16:48:20 CEST 2007

Quoting Corey Osgood <corey.osgood at gmail.com>:

> As far as the boot issue goes, can you drop into i82801xx_pci.c and put
> in printks where pci_init() starts and ends, something like "entering
> pci_init()" and "leaving pci_init()", and see what happens? I also see
> i82801db has ".ops_pci          = 0," in the pci_driver struct, but that
> shouldn't affect anything (just setting subsystem IDs, I think). And try
> commenting out that block of code with the note about the i82801er
> commenting it out as well.  I'll try to look into this further over the
> weekend, see what I can come up with.

Thanks Corey and Uwe for the feedback. I will work on those changes.  
As far as the    PCI to PCI Bridge issue, thats how I traced the  
problem is with a bunch of print calls. Ccheck out this snip of the  
lest boot log:

Done allocating resources.
Enabling resources...
PCI: 00:00.0 cmd <- 146
PCI: 00:1d.0 cmd <- 141
PCI: 00:1d.1 cmd <- 141
PCI: 00:1d.2 cmd <- 141
PCI: 00:1d.7 subsystem <- 00/00
PCI: 00:1d.7 cmd <- 142
PCI: 00:1e.0 bridge ctrl <- 0003
PCI: 00:1e.0 test1 pre ctrl <- 8080  // parity error
PCI: 00:1e.0 test1 post ctrl <- c080 // Should clear to 0080, now it  
has a serr error and parity error??
PCI: 00:1e.0 test2 pre ctrl <- 2280
PCI: 00:1e.0 test2 post ctrl <- 0280 // cleared Good!
PCI: 00:1e.0 cmd <- 141

If you check out the pci_bus_enable_resources() function in  
pci_device.c i put these tests right before it calls the  
pci_dev_enable_resources() function. The tests were to clear the serr  
and parity error bits from Primary Device Status Register 0x06 and  
Secondary Status Register 0x1E. As you can see above the bits are not  
clearing from the Primary Device Status Register 0x06 and they are  
from the Secondary Status Register 0x1E. Then what happens is in the  
pci_dev_enable_resources() function it goes enable the serr and parity  
checking on the Command Register 0x04 and that is where it chokes. I  
am assuming it is because the bits are not clearing from the Primary  
Device Status Register 0x06. But, why won't it let me clear these  
bits? Note: On these bits your supposed to write a "1" to them to  
clear them back to 0.  HELP??

Thanks - Joe

More information about the coreboot mailing list