[LinuxBIOS] RCA RM4100 almost running - help

Corey Osgood corey.osgood at gmail.com
Tue Sep 4 09:47:51 CEST 2007

Joseph Smith wrote:
> Quoting Corey Osgood <corey.osgood at gmail.com>:
>> Joseph Smith wrote:
>>> Hello,
>>> I almost have the system I have been woring on for so long now running
>>> on the console (vga is next). Here is a recap of my hardware:
>>> i82830 Northbridge
>>> i82801db Southbridge (using i82801XX)
>>> SMSC lpc47m192 Superio (using smscsuperio)
>> Great news!
>>> For some reason it keeps restarting over and over again right after
>>> the "SMBus controller enabled" message (see below). Any ideas what
>>> could be causing this?
>> Check that there isn't a GPIO (usually GP3) that's set to reboot the
>> system automatically when the timer runs up. If there is, it needs to be
>> disabled prior to ram init. Also, have you run ram_check to make sure
>> that your ram is initializing correctly?
>> -Corey
> In my Config.lb I have:
> device pnp 2e.7 off end # GAME_MIDI_GIPO1
> device pnp 2e.8 off end # GPIO2
> device pnp 2e.9 off end # GPIO3
> device pnp 2e.a off end # ACPI
> They seem to be off is that what you mean?

Those only affect LB after the ram has been initialized. You'd have to
manually disable it in pre-ram if that were the problem, but I think
it's much more likely the below. I've only seen GPIO resets on Via
hardware, so you're probably safe.

> Ok, I ran it with:
> /* Check RAM. */
> ram_check(0, 640 * 1024);
> What does this "Fail" mean? How do I fix this? Does this have anything
> to do with the fact that the memory (128MB) is embedded into the board
> (shows on original bios in slot 01) and does not have SPD? 

No, this means that your ram isn't being initialized correctly
somewhere. Start by checking that your northbridge timing registers are
set correctly, drbs set correctly, etc. As long as the init itself
follows the same procedure as the 440bx and 810, that should be correct.
Comparing lspci -xxx -s 0:0.0 and dump_dev(0) (from debug.c) might also
provide some help.


More information about the coreboot mailing list