[LinuxBIOS] addr_offset help

Corey Osgood corey.osgood at gmail.com
Sat Sep 1 05:25:35 CEST 2007

Joseph Smith wrote:
> Quoting Corey Osgood <corey.osgood at gmail.com>:
>> Joseph Smith wrote:
>>> Can someone explain the significance of the  addr_offset variable in
>>> raminit.c on the i440bx and i82810? Also why is this set to 0x1d0 for
>>> the Mode register set (MRS)?
>>> Thanks - Joe
>> MRS is a setting within the ram that's set by reading from a certain
>> location while the northbridge is in MRS mode. It essentially tells the
>> ram what timings to run at. For the most part, the only values you'll
>> ever need for SDRAM are 0x1d0 for CL3 and 0x150 for CL2, but DDR and
>> DDR2 make more advanced use of MRS and E(xtended)MRS. Read the JEDEC
>> standard for more info.
>> -Corey
> Thanks Corey, that makes sense. Not sure how it tells the memory what
> timings to run at though. Does it tell the northbridge what timings to
> run at?
> Thanks - Joe

No. The northbridge should have the timing programmed in to some
register(s). The ram then needs to be told *the same* timings that the
northbridge is told for correct operation, otherwise you end up with
them trying to run out of sync. The memory is told what timings to run
at by putting the northbridge (which also puts the ram) into MRS mode
and reading from an offset, one of the two I've given above. The values
are derived from the bits explained here:
http://www.jedec.org/download/search/3_11_05_01R12.pdf (page 6). You can
see there that those values also correspond with sequential burst and a
burst length of 2 (which I didn't know until I looked this up!). In the
440bx and i810 ports we use CL3, so it should be safe for any memory
stick, optimizing memory timings should be one of those things to do
after everything else works, IMO.


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