[LinuxBIOS] [PATCH] flashrom: add MX25L4005 erase/write support
Carl-Daniel Hailfinger
c-d.hailfinger.devel.2006 at gmx.net
Thu Oct 18 02:33:36 CEST 2007
On 18.10.2007 02:28, Carl-Daniel Hailfinger wrote:
> On 18.10.2007 02:08, Stefan Reinauer wrote:
>
>> * Carl-Daniel Hailfinger <c-d.hailfinger.devel.2006 at gmx.net> [071018 01:59]:
>>
>>
>>> My new version is way more generic and hopefully works as well.
>>> Can you test and give me an Acked-by: line?
>>>
>>>
>>
>> I did not test, but please check this in. We can and will fix and
>> improve this later as problems or ideas occur...
>>
>>
>
> OK. Harald, please check out the code currently in svn and test if it
> works for you.
>
And if that works, can you also try the following patch against current svn?
Index: spi.c
===================================================================
--- spi.c (Revision 2874)
+++ spi.c (Arbeitskopie)
@@ -270,17 +270,9 @@
generic_spi_write_enable();
/* Send CE (Chip Erase) */
generic_spi_command(1, 0, cmd, NULL);
- /* The chip needs some time for erasing, the MX25L4005A has a maximum
- * time of 7.5 seconds.
- * FIXME: Check the status register instead
- * Do we have to check the status register before calling
- * write_disable()? The data sheet suggests we don't have to call
- * write_disable() at all because WEL is reset automatically.
+ /* Wait until the Write-In-Progress bit is cleared */
while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
sleep(1);
- */
- generic_spi_write_disable();
- sleep(8);
return 0;
}
@@ -294,17 +286,9 @@
bios[256 * block + i] = buf[256 * block + i];
}
outb(0, it8716f_flashport);
- /* The chip needs some time for page program, the MX25L4005A has a
- * maximum time of 5 ms.
- * FIXME: Check the status register instead.
- * Do we have to check the status register before calling
- * write_disable()? The data sheet suggests we don't have to call
- * write_disable() at all because WEL is reset automatically.
+ /* Wait until the Write-In-Progress bit is cleared */
while (generic_spi_read_status_register() & JEDEC_RDSR_BIT_WIP)
usleep(1000);
- */
- generic_spi_write_disable();
- usleep(5000);
}
void generic_spi_page_program(int block, uint8_t *buf, uint8_t *bios)
More information about the coreboot
mailing list