[LinuxBIOS] General question about reset vectors

Marc Jones marc.jones at amd.com
Wed Oct 10 01:03:08 CEST 2007

Gabe Black wrote:
>     Hi. I'm extending the m5 simulator (www.m5sim.org) to support x86_64 
> and am trying to figure out exactly how the boot process should work. 
> According to both the AMD and Intel manuals, the cpu resets with the CS 
> base at 0xFFFF0000, the CS selector at 0xF000, and the IP at 0xFFF0 
> which means that the first instruction is fetched from physical memory 
> address 0xFFFFFFF0. In all the other references I've found, however, the 
> BIOS reset vector is described as being at 0xFFFF0. I used a hexeditor 
> on a few BIOS images, and it seems that the first instruction at that 
> reset vector is doing a far jump to CS selector 0xF000. This would keep 
> the CS selector the same, but it would cause the CS base to be 
> overwritten and instruction fetching to occur in the lower regions of 
> memory. I'm assuming that the BIOS ROM is mapped into memory at both the 
> top and bottom of the 32 bit address space, but there are very little 
> information of this upper mapping. Could someone please explain to me 
> how this is supposed to work? I need to know in enough detail to be able 
> to implement it myself, but I also don't want to be too specific and 
> limit the systems that I can simulate.
> Gabe Black


You are correct. The southbridge has to decode both 0xFFFFFFF0 and 
0xF000:0xFFF0 accesses to the flash ROM. On a legacy BIOS, once memory 
is initialized the BIOS is typically shadowed at 0xF000:0x0000(0xF0000) 
and the ROM is still available at 0xFFFFFFFF-ROMsize.


Marc Jones
Senior Firmware Engineer
(970) 226-9684 Office
mailto:Marc.Jones at amd.com

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