[LinuxBIOS] Question about protect mode?

Feng, Libo Libo.Feng at amd.com
Thu May 31 04:45:19 CEST 2007


Hi, Mr. Juergen Beisert, 

I mean that, just after power on, processor leaves the reset state, the first instruction is fetched from 0xFFFFFFF0, the address may be led to LPC, X-BUS or PCI. From other people's reply, it seems an external jumper decides the configuration, then chipset decoding logic leads the address to the right place. My understanding is correct?


Best Regards

??? Feng Libo @ AMD  Ext: 20906
Mobile Phone: 13683249071
Office Phone: 0086-010-62801406

-----Original Message-----
From: Juergen Beisert [mailto:juergen127 at kreuzholzen.de] 
Sent: Wednesday, May 30, 2007 7:27 PM
To: linuxbios at linuxbios.org
Cc: Feng, Libo
Subject: Re: [LinuxBIOS] Question about protect mode?

On Wednesday 30 May 2007 12:20, Feng, Libo wrote:
> I am also confused a little. The propriety BIOS runs in the real mode, 
> how does it test the memory beyond 1MB?

It switches also into the Linear Flat Mode. After the test is done it switches back to realmode.

> Another question is BIOS ROM can attach to XBUS, LPC, someone told me, 
> even PCI, how dose the address forward to the location?

At what time it accesses this devices? At system start? Or when something like DOS runs?
At system start see above.

When DOS runs? Hmmm. There are ways to setup all segment registers to real mode limits except for one, the ES. This one you could setup for baseaddress 0 and limit 4GiB. With this setting you could run real mode code, and whenever you like access addresses beyond 1MiB you simply use the segment override es:<blablub> for this mnemonic. But this only works within assembler. Its a solution, but an ugly one.
Another way is to switch into pm for every access beyond 1MiB and switch back to real mode when its done. This is the way some BIOSs goes to copy chunks of memory content from below 1MiB to above 1MiB.

Juergen








More information about the coreboot mailing list