[LinuxBIOS] r323 - in LinuxBIOSv3: arch/x86 include/arch/x86
svn at openbios.org
svn at openbios.org
Sat May 19 10:44:14 CEST 2007
Author: stepan
Date: 2007-05-19 10:44:14 +0200 (Sat, 19 May 2007)
New Revision: 323
Added:
LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S
LinuxBIOSv3/include/arch/x86/amd_geodelx.h
Log:
This patch adds CAR support for LX, as well as the include file. It
builds but is not tested.
Signed-off-by: Ronald G. Minnich <rminnich at gmail.com>
Acked-by: Stefan Reinauer <stepan at coresystems.de>
Added: LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S
===================================================================
--- LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S (rev 0)
+++ LinuxBIOSv3/arch/x86/stage0_amd_geodelx.S 2007-05-19 08:44:14 UTC (rev 323)
@@ -0,0 +1,411 @@
+##
+## This file is part of the LinuxBIOS project.
+##
+## Copyright (C) 2000,2007 Ronald G. Minnich <rminnich at gmail.com>
+##
+## Copyright (C) 2005 Eswar Nallusamy, LANL
+##
+## Copyright (C) 2005 Tyan
+## Written by Yinghai Lu <yhlu at tyan.com> for Tyan.
+##
+## Copyright (C) 2007 coresystems GmbH
+## Written by Stefan Reinauer <stepan at coresystems.de> for coresystems GmbH.
+##
+## Copyright (C) 2007 Advanced Micro Devices
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+## GNU General Public License for more details.
+##
+## You should have received a copy of the GNU General Public License
+## along with this program; if not, write to the Free Software
+## Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+##
+
+# init code - switch cpu to pmode and enable cache as ram.
+
+#include "macros.h"
+#include <amd_geodelx.h>
+
+#define LX_STACK_BASE CONFIG_DCACHE_RAM_BASE /* this is where the DCache will be mapped and be used as stack, It would be cool if it was the same base as LinuxBIOS normal stack */
+#define LX_STACK_END LX_STACK_BASE+(CONFIG_DCACHE_RAM_SIZE-4)
+
+#define LX_NUM_CACHELINES 0x080 /* there are 128lines per way */
+#define LX_CACHELINE_SIZE 0x020 /* there are 32bytes per line */
+#define LX_CACHEWAY_SIZE (LX_NUM_CACHELINES * LX_CACHELINE_SIZE)
+#define CR0_CD 0x40000000 /* bit 30 = Cache Disable */
+#define CR0_NW 0x20000000 /* bit 29 = Not Write Through */
+
+#define ROM_CODE_SEG 0x08
+#define ROM_DATA_SEG 0x10
+
+#define CACHE_RAM_CODE_SEG 0x18
+#define CACHE_RAM_DATA_SEG 0x20
+ .code16
+ .globl _stage0
+_stage0:
+ cli
+
+ /* save the BIST result */
+ movl %eax, %ebp;
+
+ /* thanks to kmliu at sis.com.tw for this TLB fix */
+ /* IMMEDIATELY invalidate the translation lookaside buffer before
+ * executing any further code. Even though paging is disabled we
+ * could still get false address translations due to the TLB if we
+ * didn't invalidate it.
+ */
+
+ xorl %eax, %eax
+ movl %eax, %cr3 /* Invalidate TLB */
+
+ /* switch to protected mode */
+
+ /* NOTE: With GNU assembler version 2.15.94.0.2.2 (i386-redhat-linux)
+ * using BFD version 2.15.94.0.2.2 20041220 this works fine without all
+ * the ld hackery and other things. So leave it as is with this comment.
+ */
+
+ data32 lgdt %cs:gdtptr
+
+ movl %cr0, %eax
+ andl $0x7FFAFFD1, %eax /* PG,AM,WP,NE,TS,EM,MP = 0 */
+ orl $0x60000001, %eax /* CD, NW, PE = 1 */
+ movl %eax, %cr0
+
+ /* Restore BIST result */
+ movl %ebp, %eax
+
+
+ // port80_post (0x23) /* post 0x01 */
+ /* Now we are in protected mode. Jump to a 32 bit code segment. */
+ data32 ljmp $ROM_CODE_SEG, $protected_stage0
+ /* I am leaving this weird jump in here in the event that future gas bugs force it to be used. */
+ #.byte 0x66
+ .code32
+ #ljmp $ROM_CODE_SEG, $protected_stage0
+
+ #.code16
+ .align 4
+ .globl gdt16
+gdt16 = . - _stage0
+gdt16x:
+ .word gdt16xend - gdt16x -1 /* compute the table limit */
+ .long gdt16x
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10,flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+gdt16xend:
+
+ /* From now on we are 32bit */
+
+ .code32
+
+/* We have two gdts where we could have one. That is ok.
+ *
+ * Let's not worry about this -- optimizing gdt is pointless since we're
+ * only in it for a little bit.
+ *
+ * BTW note the trick below: The GDT points to ITSELF, and the first good
+ * descriptor is at offset 8. So you word-align the table, and then because
+ * you chose 8, you get a nice 64-bit aligned GDT entry, which is good as
+ * this is the size of the entry.
+ * Just in case you ever wonder why people do this.
+ */
+ .align 4
+ .globl gdtptr
+ .globl gdt_limit
+gdt_limit = gdt_end - gdt - 1 /* compute the table limit */
+
+gdt:
+gdtptr:
+ .word gdt_end - gdt -1 /* compute the table limit */
+ .long gdt /* we know the offset */
+ .word 0
+
+ /* selgdt 0x08, flat code segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x10,flat data segment */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+
+ /* selgdt 0x18, flat code segment for CAR */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x9b, 0xcf, 0x00
+
+ /* selgdt 0x20,flat data segment for CAR */
+ .word 0xffff, 0x0000
+ .byte 0x00, 0x93, 0xcf, 0x00
+gdt_end:
+
+/*
+ * When we come here we are in protected mode. We expand
+ * the stack and copies the data segment from ROM to the
+ * memory.
+ *
+ * After that, we call the chipset bootstrap routine that
+ * does what is left of the chipset initialization.
+ *
+ * NOTE: Aligned to 4 so that we are sure that the prefetch
+ * cache will be reloaded.
+ */
+
+ .align 4
+ .globl protected_stage0
+protected_stage0:
+ //This code was used by v2. TODO
+ lgdt %cs:gdtptr
+ ljmp $ROM_CODE_SEG, $__protected_stage0
+
+.globl __protected_stage0
+__protected_stage0:
+ /* Save the BIST value */
+ movl %eax, %ebp
+
+ port80_post (0x01) /* post 0x01 */
+
+ movw $ROM_DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+ movw %ax, %fs
+ movw %ax, %gs
+
+ /* Restore the BIST value to %eax */
+ movl %ebp, %eax
+
+.align 4
+ /* here begins CAR support */
+ /* this particular code is straight from LinuxBIOS V2 */
+/***************************************************************************
+/**
+/** DCacheSetup
+/**
+/** Setup data cache for use as RAM for a stack.
+/**
+/***************************************************************************/
+DCacheSetup:
+
+ invd
+ /* set cache properties */
+ movl $CPU_RCONF_DEFAULT, %ecx
+ rdmsr
+ movl $0x010010000, %eax /*1MB system memory in write back 1|00100|00 */
+ wrmsr
+
+ /* in LX DCDIS is set after POR which disables the cache..., clear this bit */
+ movl CPU_DM_CONFIG0,%ecx
+ rdmsr
+ andl $(~(DM_CONFIG0_LOWER_DCDIS_SET)), %eax /* TODO: make consistent with i$ init, either whole reg = 0, or just this bit... */
+ wrmsr
+
+ /* get cache timing params from BIOS config data locations and apply */
+ /* fix delay controls for DM and IM arrays */
+ /* fix delay controls for DM and IM arrays */
+ movl $CPU_BC_MSS_ARRAY_CTL0, %ecx
+ xorl %edx, %edx
+ movl $0x2814D352, %eax
+ wrmsr
+
+ movl $CPU_BC_MSS_ARRAY_CTL1, %ecx
+ xorl %edx, %edx
+ movl $0x1068334D, %eax
+ wrmsr
+
+ movl $CPU_BC_MSS_ARRAY_CTL2, %ecx
+ movl $0x00000106, %edx
+ movl $0x83104104, %eax
+ wrmsr
+
+ movl $GLCP_FIFOCTL, %ecx
+ rdmsr
+ movl $0x00000005, %edx
+ wrmsr
+
+ /* Enable setting */
+ movl $CPU_BC_MSS_ARRAY_CTL_ENA, %ecx
+ xorl %edx, %edx
+ movl $0x01, %eax
+ wrmsr
+
+ /* Get cleaned up. */
+ xorl %edi, %edi
+ xorl %esi, %esi
+ xorl %ebp, %ebp
+
+ /* DCache Ways0 through Ways7 will be tagged for LX_STACK_BASE + CONFIG_DCACHE_RAM_SIZE for holding stack */
+ /* remember, there is NO stack yet... */
+
+ /* Tell cache we want to fill WAY 0 starting at the top */
+ xorl %edx, %edx
+ xorl %eax, %eax
+ movl $CPU_DC_INDEX, %ecx
+ wrmsr
+
+ /* startaddress for tag of Way0: ebp will hold the incrementing address. dont destroy! */
+ movl $LX_STACK_BASE, %ebp /* init to start address */
+ orl $1, %ebp /* set valid bit and tag for this Way (B[31:12] : Cache tag value for line/way curr. selected by CPU_DC_INDEX */
+
+ /* start tag Ways 0 with 128 lines with 32bytes each: edi will hold the line counter. dont destroy! */
+ movl $LX_NUM_CACHELINES, %edi
+DCacheSetupFillWay:
+
+ /* fill with dummy data: zero it so we can tell it from PCI memory space (returns FFs). */
+ /* We will now store a line (32 bytes = 4 x 8bytes = 4 quadWords) */
+ movw $0x04, %si
+ xorl %edx, %edx
+ xorl %eax, %eax
+ movl $CPU_DC_DATA, %ecx
+DCacheSetup_quadWordLoop:
+ wrmsr
+ decw %si
+ jnz DCacheSetup_quadWordLoop
+
+ /* Set the tag for this line, need to do this for every new cache line to validate it! */
+ /* accessing CPU_DC_TAG_I makes the LINE field in CPU_DC_INDEX increment and thus cont. in the next cache line... */
+ xorl %edx, %edx
+ movl %ebp, %eax
+ movl $CPU_DC_TAG, %ecx
+ wrmsr
+
+ /* switch to next line */
+ /* lines are in Bits10:4 */
+ /* when index is crossing 0x7F -> 0x80 writing a RSVD bit as 0x80 is not a valid CL anymore! */
+ movl $CPU_DC_INDEX, %ecx
+ rdmsr
+ addl $0x010, %eax /* TODO: prob. would be more elegant to calc. this from counter var edi... */
+ wrmsr
+
+ decl %edi
+ jnz DCacheSetupFillWay
+
+ /* 1 Way has been filled, forward start address for next Way, terminate if we have reached end of desired address range */
+ addl $LX_CACHEWAY_SIZE, %ebp
+ cmpl $LX_STACK_END, %ebp
+ jge leave_DCacheSetup
+ movl $LX_NUM_CACHELINES, %edi
+
+ /* switch to next way */
+ movl $CPU_DC_INDEX, %ecx
+ rdmsr
+ addl $0x01, %eax
+ andl $0xFFFFF80F, %eax /* lets be sure: reset line index Bits10:4 */
+ wrmsr
+
+ jmp DCacheSetupFillWay
+
+leave_DCacheSetup:
+ xorl %edi, %edi
+ xorl %esi, %esi
+ xorl %ebp, %ebp
+
+ /* Disable the cache, but ... DO NOT INVALIDATE the tags. */
+ /* Memory reads and writes will all hit in the cache. */
+ /* Cache updates and memory write-backs will not occur ! */
+ movl %cr0, %eax
+ orl $(CR0_CD + CR0_NW), %eax /* set the CD and NW bits */
+ movl %eax, %cr0
+
+ /* Now point sp to the cached stack. */
+ /* The stack will be fully functional at this location. No system memory is required at all ! */
+ /* set up the stack pointer */
+ movl $LX_STACK_END, %eax
+ movl %eax, %esp
+
+ /* test the stack*/
+ movl $0x0F0F05A5A, %edx
+ pushl %edx
+ popl %ecx
+ cmpl %ecx, %edx
+ je DCacheSetupGood
+ movb $0xC5, %al
+ outb %al, $0x80
+DCacheSetupBad:
+ hlt /* issues */
+ jmp DCacheSetupBad
+DCacheSetupGood:
+
+ /* If you wanted to maintain the stack in memory you would need to set the tags as dirty
+ so the wbinvd would push out the old stack contents to memory */
+ /* Clear the cache, the following code from crt0.S.lb will setup a new stack*/
+ wbinvd
+
+ /* at this point, CAR should be working */
+ movl $(LX_STACK_END), %eax
+ movl %eax, %esp
+
+ /* Load a different set of data segments */
+ movw $CACHE_RAM_DATA_SEG, %ax
+ movw %ax, %ds
+ movw %ax, %es
+ movw %ax, %ss
+
+lout:
+
+ /* Restore the BIST result */
+ movl %ebp, %eax
+ /* We need to set ebp ? No need */
+ movl %esp, %ebp
+ pushl %eax /* bist */
+ call stage1_main
+ /* We will not go back */
+fixed_mtrr_msr:
+ .long 0x250, 0x258, 0x259
+ .long 0x268, 0x269, 0x26A
+ .long 0x26B, 0x26C, 0x26D
+ .long 0x26E, 0x26F
+var_mtrr_msr:
+ .long 0x200, 0x201, 0x202, 0x203
+ .long 0x204, 0x205, 0x206, 0x207
+ .long 0x208, 0x209, 0x20A, 0x20B
+ .long 0x20C, 0x20D, 0x20E, 0x20F
+ .long 0x000 /* NULL, end of table */
+
+# Reset vector.
+
+/*
+ RVECTOR: size of reset vector, default is 0x10
+ RESRVED: size of vpd code, default is 0xf0
+ BOOTBLK: size of bootblock code, default is 0x1f00 (8k-256b)
+*/
+
+SEGMENT_SIZE = 0x10000
+RVECTOR = 0x00010
+# Due to YET ANOTHER BUG in GNU bintools, you can NOT have a code16 here.
+# I think we should leave it this way forever, as the bugs come and
+# go -- and come again.
+# .code16
+# .section ".rom.text"
+.section ".reset", "ax"
+ .globl _resetjump
+_resetjump:
+ /* GNU bintools bugs again. This jumps to stage0 - 2. Sigh. */
+# jmp _stage0
+ .byte 0xe9
+ .int _stage0 - ( . + 2 )
+ /* Note: The above jump is hand coded to work around bugs in binutils.
+ * 5 byte are used for a 3 byte instruction. This works because x86
+ * is little endian and allows us to use supported 32bit relocations
+ * instead of the weird 16 bit relocations that binutils does not
+ * handle consistenly between versions because they are used so rarely.
+ */
+.byte 0
+
+# Date? ID string? We might want to put something else in here.
+.ascii DATE
+
+# Checksum.
+#.word 0
Added: LinuxBIOSv3/include/arch/x86/amd_geodelx.h
===================================================================
--- LinuxBIOSv3/include/arch/x86/amd_geodelx.h (rev 0)
+++ LinuxBIOSv3/include/arch/x86/amd_geodelx.h 2007-05-19 08:44:14 UTC (rev 323)
@@ -0,0 +1,562 @@
+/*
+ * This file is part of the LinuxBIOS project.
+ *
+ * Copyright (C) 2006 Indrek Kruusa <indrek.kruusa at artecdesign.ee>
+ * Copyright (C) 2006 Ronald G. Minnich <rminnich at gmail.com>
+ * Copyright (C) 2006 Stefan Reinauer <stepan at coresystems.de>
+ * Copyright (C) 2006 Andrei Birjukov <andrei.birjukov at artecdesign.ee>
+ * Copyright (C) 2007 Advanced Micro Devices, Inc.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program; if not, write to the Free Software
+ * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+ */
+
+#ifndef CPU_AMD_LXDEF_H
+#define CPU_AMD_LXDEF_H
+
+#define CPU_ID_1_X 0x00000560 /* Stepping ID 1.x CPUbug fix to change it to 5A0 */
+#define CPU_ID_2_0 0x000005A1
+#define CPU_ID_3_0 0x000005A2
+
+#define CPU_REV_1_0 0x010
+#define CPU_REV_1_1 0x011
+#define CPU_REV_2_0 0x020
+#define CPU_REV_2_1 0x021
+#define CPU_REV_2_2 0x022
+#define CPU_REV_C_0 0x030
+#define CPU_REV_C_1 0x031
+#define CPU_REV_C_2 0x032 /* 3.2 part was never produced ... */
+#define CPU_REV_C_3 0x033
+
+/* MSR routing as follows*/
+/* MSB = 1 means not for CPU*/
+/* next 3 bits 1st port*/
+/* next3 bits next port if through an GLIU*/
+/* etc...*/
+
+/* GLIU0 ports */
+#define GL0_GLIU0 0
+#define GL0_MC 1
+#define GL0_GLIU1 2
+#define GL0_CPU 3
+#define GL0_VG 4
+#define GL0_GP 5
+
+/* GLIU1 ports */
+#define GL1_GLIU0 1
+#define GL1_DF 2
+#define GL1_GLCP 3
+#define GL1_PCI 4
+#define GL1_VIP 5
+#define GL1_AES 6
+
+#define MSR_GLIU0 (GL0_GLIU0 << 29) + (1 << 28) /* 1000xxxx, To get on GeodeLink one bit has to be set */
+#define MSR_MC (GL0_MC << 29) /* 2000xxxx */
+#define MSR_GLIU1 (GL0_GLIU1 << 29) /* 4000xxxx */
+#define MSR_CPU (GL0_CPU << 29) /* 0000xxxx this is not used for BIOS since code executing on CPU doesn't need to be routed */
+#define MSR_VG (GL0_VG << 29) /* 8000xxxx */
+#define MSR_GP (GL0_GP << 29) /* A000xxxx */
+
+#define MSR_DF ((GL1_DF << 26) + MSR_GLIU1) /* 4800xxxx */
+#define MSR_GLCP ((GL1_GLCP << 26) + MSR_GLIU1) /* 4C00xxxx */
+#define MSR_PCI ((GL1_PCI << 26) + MSR_GLIU1) /* 5000xxxx */
+#define MSR_VIP ((GL1_VIP << 26) + MSR_GLIU1) /* 5400xxxx */
+#define MSR_AES ((GL1_AES << 26) + MSR_GLIU1) /* 5800xxxx */
+#define MSR_FG MSR_GLCP
+
+/*GeodeLink Interface Unit 0 (GLIU0) port0*/
+
+#define GLIU0_GLD_MSR_CAP (MSR_GLIU0 + 0x2000)
+#define GLIU0_GLD_MSR_ERROR (MSR_GLIU0 + 0x2003)
+#define GLIU0_GLD_MSR_PM (MSR_GLIU0 + 0x2004)
+
+#define GLIU0_DESC_BASE (MSR_GLIU0 + 0x20)
+#define GLIU0_CAP (MSR_GLIU0 + 0x86)
+#define GLIU0_GLD_MSR_COH (MSR_GLIU0 + 0x80)
+
+#define GLIU0_ARB (MSR_GLIU0 + 0x82)
+#define ARB_UPPER_QUACK_EN_SET (1 << 31)
+#define ARB_UPPER_DACK_EN_SET (1 << 28)
+
+/* Memory Controller GLIU0 port 1*/
+
+#define MC_GLD_MSR_CAP (MSR_MC + 0x2000)
+#define MC_GLD_MSR_PM (MSR_MC + 0x2004)
+
+#define MC_CF07_DATA (MSR_MC + 0x18)
+#define CF07_UPPER_D1_SZ_SHIFT 28
+#define CF07_UPPER_D1_MB_SHIFT 24
+#define CF07_UPPER_D1_CB_SHIFT 20
+#define CF07_UPPER_D1_PSZ_SHIFT 16
+#define CF07_UPPER_D0_SZ_SHIFT 12
+#define CF07_UPPER_D0_MB_SHIFT 8
+#define CF07_UPPER_D0_CB_SHIFT 4
+#define CF07_UPPER_D0_PSZ_SHIFT 0
+
+#define CF07_LOWER_REF_INT_SHIFT 8
+#define CF07_LOWER_LOAD_MODE_DDR_SET (1 << 28)
+#define CF07_LOWER_LOAD_MODE_DLL_RESET (1 << 27)
+#define CF07_LOWER_EMR_QFC_SET (1 << 26)
+#define CF07_LOWER_EMR_DRV_SET (1 << 25)
+#define CF07_LOWER_REF_TEST_SET (1 << 3)
+#define CF07_LOWER_PROG_DRAM_SET (1 << 0)
+
+#define MC_CF8F_DATA (MSR_MC + 0x19)
+#define CF8F_UPPER_XOR_BS_SHIFT 19
+#define CF8F_UPPER_XOR_MB0_SHIFT 18
+#define CF8F_UPPER_XOR_BA1_SHIFT 17
+#define CF8F_UPPER_XOR_BA0_SHIFT 16
+#define CF8F_UPPER_REORDER_DIS_SET (1 << 8)
+#define CF8F_LOWER_CAS_LAT_SHIFT 28
+#define CF8F_LOWER_ACT2ACTREF_SHIFT 24
+#define CF8F_LOWER_ACT2PRE_SHIFT 20
+#define CF8F_LOWER_PRE2ACT_SHIFT 16
+#define CF8F_LOWER_ACT2CMD_SHIFT 12
+#define CF8F_LOWER_ACT2ACT_SHIFT 8
+#define CF8F_UPPER_HOI_LOI_SET (1 << 1)
+
+#define MC_CF1017_DATA (MSR_MC + 0x1A)
+#define CF1017_LOWER_WR_TO_RD_SHIFT 28
+#define CF1017_LOWER_RD_TMG_CTL_SHIFT 24
+#define CF1017_LOWER_REF2ACT_SHIFT 16
+#define CF1017_LOWER_PM1_UP_DLY_SET (1 << 8)
+#define CF1017_LOWER_WR2DAT_SHIFT 0
+
+#define MC_CFCLK_DBUG (MSR_MC + 0x1D)
+
+#define CFCLK_UPPER_MTST_B2B_DIS_SET (1 << 2)
+#define CFCLK_UPPER_MTST_RBEX_EN_SET (1 << 1)
+#define CFCLK_UPPER_MTEST_EN_SET (1 << 0)
+
+#define CFCLK_LOWER_FORCE_PRE_SET (1 << 16)
+#define CFCLK_LOWER_TRISTATE_DIS_SET (1 << 12)
+#define CFCLK_LOWER_MASK_CKE_SET1 (1 << 9)
+#define CFCLK_LOWER_MASK_CKE_SET0 (1 << 8)
+#define CFCLK_LOWER_SDCLK_SET (0x0F << 0)
+
+#define MC_CF_RDSYNC (MSR_MC + 0x1F)
+#define MC_CF_PMCTR (MSR_MC + 0x20)
+
+/* GLIU1 GLIU0 port2*/
+
+#define GLIU1_GLD_MSR_CAP (MSR_GLIU1 + 0x2000)
+#define GLIU1_GLD_MSR_ERROR (MSR_GLIU1 + 0x2003)
+#define GLIU1_GLD_MSR_PM (MSR_GLIU1 + 0x2004)
+
+#define GLIU1_GLD_MSR_COH (MSR_GLIU1 + 0x80)
+#define GLIU1_PORT_ACTIVE (MSR_GLIU1 + 0x81)
+#define GLIU1_ARB (MSR_GLIU1 + 0x82)
+
+/* CPU ; does not need routing instructions since we are executing there.*/
+
+#define CPU_GLD_MSR_CAP 0x2000
+#define CPU_GLD_MSR_CONFIG 0x2001
+#define CPU_GLD_MSR_PM 0x2004
+
+#define CPU_GLD_MSR_DIAG 0x2005
+#define DIAG_SEL1_MODE_SHIFT 16
+#define DIAG_SEL1_SET (1 << 31)
+#define DIAG_SEL0__MODE_SHIFT 0
+#define DIAG_SET0_SET (1 << 15)
+
+#define CPU_PF_CONF 0x1100
+#define RETURN_STACK_ENABLE_SET (1 << 4)
+#define PF_CONF_CC_L1 (1 << 0)
+#define CPU_PF_INVD 0x1102
+#define PF_RS_INVD_SET (1 << 1)
+#define PF_CC_INVD_SET (1 << 0)
+#define CPU_PF_BIST 0x1140
+
+#define CPU_XC_CONFIG 0x1210
+#define XC_CONFIG_SUSP_ON_HLT (1 << 0)
+#define XC_CONFIG_SUSP_ON_PAUSE (1 << 1)
+
+#define CPU_ID_CONFIG 0x1250
+#define ID_CONFIG_SERIAL_SET (1 << 0)
+
+#define CPU_AC_MSR 0x1301
+
+/* SMM*/
+#define CPU_AC_SMM_CTL 0x1301
+#define SMM_NMI_EN_SET (1 << 0)
+#define SMM_SUSP_EN_SET (1 << 1)
+#define NEST_SMI_EN_SET (1 << 2)
+#define SMM_INST_EN_SET (1 << 3)
+#define INTL_SMI_EN_SET (1 << 4)
+#define EXTL_SMI_EN_SET (1 << 5)
+
+#define CPU_EX_BIST 0x1428
+
+ /*IM*/
+#define CPU_IM_CONFIG 0x1700
+#define IM_CONFIG_LOWER_SERIAL_SET (1 << 2)
+#define IM_CONFIG_LOWER_L0WE_SET (1 << 6)
+#define IM_CONFIG_LOWER_ICD_SET (1 << 8)
+#define IM_CONFIG_LOWER_EBE_SET (1 << 10)
+#define IM_CONFIG_LOWER_ABSE_SET (1 << 11)
+#define IM_CONFIG_LOWER_QWT_SET (1 << 20)
+
+#define CPU_IC_INDEX 0x1710
+#define CPU_IC_DATA 0x1711
+#define CPU_IC_TAG 0x1712
+#define CPU_IC_TAG_I 0x1713
+#define CPU_ITB_INDEX 0x1720
+#define CPU_ITB_LRU 0x1721
+#define CPU_ITB_ENTRY 0x1722
+#define CPU_ITB_ENTRY_I 0x1723
+#define CPU_IM_BIST_TAG 0x1730
+#define CPU_IM_BIST_DATA 0x1731
+/*DM MSR MAP*/
+#define CPU_DM_CONFIG0 0x1800
+#define DM_CONFIG0_UPPER_WSREQ_SHIFT 12
+#define DM_CONFIG0_LOWER_EVCTONRPL_SET (1 << 14)
+#define DM_CONFIG0_LOWER_WBINVD_SET (1<<5)
+#define DM_CONFIG0_LOWER_DCDIS_SET (1 << 8)
+#define DM_CONFIG0_LOWER_MISSER_SET (1<<1)
+
+#define CPU_RCONF_DEFAULT 0x1808
+#define RCONF_DEFAULT_UPPER_ROMRC_SHIFT 24
+#define RCONF_DEFAULT_UPPER_ROMBASE_SHIFT 4
+#define RCONF_DEFAULT_UPPER_DEVRC_HI_SHIFT 0
+#define RCONF_DEFAULT_LOWER_DEVRC_LOW_SHIFT 28
+#define RCONF_DEFAULT_LOWER_SYSTOP_SHIFT 8
+#define RCONF_DEFAULT_LOWER_SYSRC_SHIFT 0
+
+#define CPU_RCONF_BYPASS 0x180A
+#define CPU_RCONF_A0_BF 0x180B
+#define CPU_RCONF_C0_DF 0x180C
+#define CPU_RCONF_E0_FF 0x180D
+#define CPU_RCONF_SMM 0x180E
+#define RCONF_SMM_UPPER_SMMTOP_SHIFT 12
+#define RCONF_SMM_UPPER_RCSMM_SHIFT 0
+#define RCONF_SMM_LOWER_SMMBASE_SHIFT 12
+#define RCONF_SMM_LOWER_RCNORM_SHIFT 0
+#define RCONF_SMM_LOWER_EN_SET (1<<8)
+
+#define CPU_RCONF_DMM 0x180F
+#define RCONF_DMM_UPPER_DMMTOP_SHIFT 12
+#define RCONF_DMM_UPPER_RCDMM_SHIFT 0
+#define RCONF_DMM_LOWER_DMMBASE_SHIFT 12
+#define RCONF_DMM_LOWER_RCNORM_SHIFT 0
+#define RCONF_DMM_LOWER_EN_SET (1<<8)
+
+#define CPU_RCONF0 0x1810
+#define CPU_RCONF1 0x1811
+#define CPU_RCONF2 0x1812
+#define CPU_RCONF3 0x1813
+#define CPU_RCONF4 0x1814
+#define CPU_RCONF5 0x1815
+#define CPU_RCONF6 0x1816
+#define CPU_RCONF7 0x1817
+#define CPU_CR1_MSR 0x1881
+#define CPU_CR2_MSR 0x1882
+#define CPU_CR3_MSR 0x1883
+#define CPU_CR4_MSR 0x1884
+#define CPU_DC_INDEX 0x1890
+#define CPU_DC_DATA 0x1891
+#define CPU_DC_TAG 0x1892
+#define CPU_DC_TAG_I 0x1893
+#define CPU_SNOOP 0x1894
+#define CPU_DTB_INDEX 0x1898
+#define CPU_DTB_LRU 0x1899
+#define CPU_DTB_ENTRY 0x189A
+#define CPU_DTB_ENTRY_I 0x189B
+#define CPU_L2TB_INDEX 0x189C
+#define CPU_L2TB_LRU 0x189D
+#define CPU_L2TB_ENTRY 0x189E
+#define CPU_L2TB_ENTRY_I 0x189F
+#define CPU_DM_BIST 0x18C0
+#define CPU_BC_CONF_0 0x1900
+#define TSC_SUSP_SET (1<<5)
+#define SUSP_EN_SET (1<<12)
+
+#define CPU_BC_CONF_1 0x1901
+#define CPU_BC_MSR_LOCK 0x1908
+#define CPU_BC_L2_CONF 0x1920
+#define BC_L2_ENABLE_SET (1 << 0)
+#define BC_L2_ALLOC_ENABLE_SET (1 << 1)
+#define BC_L2_DM_ALLOC_ENABLE_SET (1 << 2)
+#define BC_L2_IM_ALLOC_ENABLE_SET (1 << 3)
+#define BC_L2_INVALIDATE_SET (1 << 4)
+
+#define CPU_BC_L2_STATUS 0x1921
+#define CPU_BC_L2_INDEX 0x1922
+#define CPU_BC_L2_DATA 0x1923
+#define CPU_BC_L2_TAG 0x1924
+#define CPU_BC_L2_TAG_AUTOINC 0x1925
+#define CPU_BC_L2_BIST 0x1926
+#define BC_L2_BIST_TAG_ENABLE_SET (1 << 0)
+#define BC_L2_BIST_TAG_DRT_EN_SET (1 << 1)
+#define BC_L2_BIST_DATA_ENABLE_SET (1 << 2)
+#define BC_L2_BIST_DATA_DRT_EN_SET (1 << 3)
+#define BC_L2_BIST_MRU_ENABLE_SET (1 << 4)
+#define BC_L2_BIST_MRU_DRT_EN_SET (1 << 5)
+
+#define CPU_BC_PMODE_MSR 0x1930
+#define CPU_BC_MSS_ARRAY_CTL_ENA 0x1980
+#define CPU_BC_MSS_ARRAY_CTL0 0x1981
+#define CPU_BC_MSS_ARRAY_CTL1 0x1982
+#define CPU_BC_MSS_ARRAY_CTL2 0x1983
+#define CPU_FPU_MSR_MODE 0x1A00
+#define FPU_IE_SET (1 << 0)
+
+#define CPU_FP_UROM_BIST 0x1A03
+#define CPU_CPUID0 0x3000
+#define CPU_CPUID1 0x3001
+#define CPU_CPUID2 0x3002
+#define CPU_CPUID3 0x3003
+#define CPU_CPUID4 0x3004
+#define CPU_CPUID5 0x3005
+#define CPU_CPUID6 0x3006
+#define CPU_CPUID7 0x3007
+#define CPU_CPUID8 0x3008
+#define CPU_CPUID9 0x3009
+#define CPU_CPUIDA 0x300A
+#define CPU_CPUIDB 0x300B
+#define CPU_CPUIDC 0x300C
+#define CPU_CPUIDD 0x300D
+#define CPU_CPUIDE 0x300E
+#define CPU_CPUIDF 0x300F
+#define CPU_CPUID10 0x3010
+#define CPU_CPUID11 0x3011
+#define CPU_CPUID12 0x3012
+#define CPU_CPUID13 0x3013
+ /* VG GLIU0 port4 */
+#define VG_GLD_MSR_CAP (MSR_VG + 0x2000)
+#define VG_GLD_MSR_CONFIG (MSR_VG + 0x2001)
+#define VG_GLD_MSR_PM (MSR_VG + 0x2004)
+#define VG_BIST (MSR_VG + 0x2010)
+/* GP GLIU0 port5*/
+#define GP_GLD_MSR_CAP (MSR_GP + 0x2000)
+#define GP_GLD_MSR_CONFIG (MSR_GP + 0x2001)
+#define GP_GLD_MSR_PM (MSR_GP + 0x2004)
+/* DF GLIU0 port6*/
+#define DF_GLD_MSR_CAP (MSR_DF + 0x2000)
+#define DF_GLD_MSR_MASTER_CONF (MSR_DF + 0x2001)
+#define DF_LOWER_LCD_SHIFT 6
+#define DF_GLD_MSR_PM (MSR_DF + 0x2004)
+#define DF_BIST (MSR_DF + 0x2005)
+/* GeodeLink Control Processor GLIU1 port3*/
+#define GLCP_GLD_MSR_CAP (MSR_GLCP + 0x2000)
+#define GLCP_GLD_MSR_CONF (MSR_GLCP + 0x2001)
+#define GLCP_GLD_MSR_SMI (MSR_GLCP + 0x2002)
+#define GLCP_GLD_MSR_ERROR (MSR_GLCP + 0x2003)
+#define GLCP_GLD_MSR_PM (MSR_GLCP + 0x2004)
+#define GLCP_DELAY_CONTROLS (MSR_GLCP + 0x0F)
+#define GLCP_SYS_RSTPLL (MSR_GLCP + 0x14) /* R/W */
+#define RSTPLL_UPPER_GLMULT_SHIFT 7
+#define RSTPLL_UPPER_GLDIV_SHIFT 6
+#define RSTPLL_UPPER_CPUMULT_SHIFT 1
+#define RSTPLL_UPPER_CPUDIV_SHIFT 0
+#define RSTPLL_LOWER_SWFLAGS_SHIFT 26
+#define RSTPLL_LOWER_SWFLAGS_MASK (0x03F << RSTPLL_LOWER_SWFLAGS_SHIFT)
+#define RSTPPL_LOWER_HOLD_COUNT_SHIFT 16
+#define RSTPPL_LOWER_COREBYPASS_SHIFT 12
+#define RSTPPL_LOWER_GLBYPASS_SHIFT 11
+#define RSTPPL_LOWER_PCISPEED_SHIFT 7
+#define RSTPPL_LOWER_BOOTSTRAP_SHIFT 1
+#define RSTPLL_LOWER_BOOTSTRAP_MASK (0x07F << RSTPLL_LOWER_BOOTSTRAP_SHIFT)
+#define RSTPPL_LOWER_GLLOCK_SET (1 << 25)
+#define RSTPPL_LOWER_CORELOCK_SET (1 << 24)
+#define RSTPPL_LOWER_LOCKWAIT_SET (1 << 15)
+#define RSTPPL_LOWER_CLPD_SET (1 << 14)
+#define RSTPPL_LOWER_COREPD_SET (1 << 13)
+#define RSTPPL_LOWER_MBBYPASS_SET (1 << 12)
+#define RSTPPL_LOWER_COREBYPASS_SET (1 << 11)
+#define RSTPPL_LOWER_LPFEN_SET (1 << 10)
+#define RSTPPL_LOWER_CPU_SEMI_SYNC_SET (1<<9)
+#define RSTPPL_LOWER_PCI_SEMI_SYNC_SET (1<<8)
+#define RSTPPL_LOWER_CHIP_RESET_SET (1<<0)
+
+#define GLCP_DOWSER (MSR_GLCP + 0x0E)
+#define GLCP_DBGCLKCTL (MSR_GLCP + 0x16)
+#define GLCP_REVID (MSR_GLCP + 0x17)
+#define GLCP_TH_OD (MSR_GLCP + 0x1E)
+#define GLCP_FIFOCTL (MSR_GLCP + 0x5E)
+#define GLCP_BIST GLCP_FIFOCTL
+#define MSR_INIT (MSR_GLCP + 0x33)
+/* GLIU1 port 4*/
+#define GLPCI_GLD_MSR_CAP (MSR_PCI + 0x2000)
+#define GLPCI_GLD_MSR_CONFIG (MSR_PCI + 0x2001)
+#define GLPCI_GLD_MSR_PM (MSR_PCI + 0x2004)
+#define GLPCI_CTRL (MSR_PCI + 0x2010)
+#define GLPCI_CTRL_UPPER_FTH_SHIFT 28
+#define GLPCI_CTRL_UPPER_RTH_SHIFT 24
+#define GLPCI_CTRL_UPPER_SBRTH_SHIFT 20
+#define GLPCI_CTRL_UPPER_RTL_SHIFT 17
+#define GLPCI_CTRL_UPPER_DTL_SHIFT 14
+#define GLPCI_CTRL_UPPER_WTO_SHIFT 11
+#define GLPCI_CTRL_UPPER_SLTO_SHIFT 10
+#define GLPCI_CTRL_UPPER_ILTO_SHIFT 8
+#define GLPCI_CTRL_UPPER_LAT_SHIFT 3
+#define GLPCI_CTRL_LOWER_IRFT_SHIFT 18
+#define GLPCI_CTRL_LOWER_IRFC_SHIFT 16
+#define GLPCI_CTRL_LOWER_ER_SET (1<<11)
+#define GLPCI_CTRL_LOWER_LDE_SET (1<<9)
+#define GLPCI_CTRL_LOWER_OWC_SET (1<<4)
+#define GLPCI_CTRL_LOWER_IWC_SET (1<<3)
+#define GLPCI_CTRL_LOWER_PCD_SET (1<<2)
+#define GLPCI_CTRL_LOWER_ME_SET (1<<0)
+
+#define GLPCI_ARB (MSR_PCI + 0x2011)
+#define GLPCI_ARB_UPPER_CR_SHIFT 28
+#define GLPCI_ARB_UPPER_R2_SHIFT 24
+#define GLPCI_ARB_UPPER_R1_SHIFT 20
+#define GLPCI_ARB_UPPER_R0_SHIFT 16
+#define GLPCI_ARB_UPPER_CH_SHIFT 12
+#define GLPCI_ARB_UPPER_H2_SHIFT 8
+#define GLPCI_ARB_UPPER_H1_SHIFT 4
+#define GLPCI_ARB_UPPER_H0_SHIFT 0
+#define GLPCI_ARB_LOWER_COV_SET (1<<23)
+#define GLPCI_ARB_LOWER_VO2_SET (1 << 22)
+#define GLPCI_ARB_LOWER_OV1_SET (1 << 21)
+#define GLPCI_ARB_LOWER_OV0_SET (1 << 20)
+#define GLPCI_ARB_LOWER_MSK2_SET (1<<18)
+#define GLPCI_ARB_LOWER_MSK1_SET (1<<17)
+#define GLPCI_ARB_LOWER_MSK0_SET (1<<16)
+#define GLPCI_ARB_LOWER_CPRE_SET (1<<11)
+#define GLPCI_ARB_LOWER_PRE2_SET (1<<10)
+#define GLPCI_ARB_LOWER_PRE1_SET (1<<9)
+#define GLPCI_ARB_LOWER_PRE0_SET (1<<8)
+#define GLPCI_ARB_LOWER_BM1_SET (1<<7)
+#define GLPCI_ARB_LOWER_BM0_SET (1<<6)
+#define GLPCI_ARB_LOWER_EA_SET (1 << 2)
+#define GLPCI_ARB_LOWER_BMD_SET (1 << 1)
+#define GLPCI_ARB_LOWER_PARK_SET (1<<0)
+
+#define GLPCI_REN (MSR_PCI + 0x2014)
+#define GLPCI_A0_BF (MSR_PCI + 0x2015)
+#define GLPCI_C0_DF (MSR_PCI + 0x2016)
+#define GLPCI_E0_FF (MSR_PCI + 0x2017)
+#define GLPCI_RC0 (MSR_PCI + 0x2018)
+#define GLPCI_RC1 (MSR_PCI + 0x2019)
+#define GLPCI_RC2 (MSR_PCI + 0x201A)
+#define GLPCI_RC3 (MSR_PCI + 0x201B)
+#define GLPCI_RC4 (MSR_PCI + 0x201C)
+#define GLPCI_RC_UPPER_TOP_SHIFT 12
+#define GLPCI_RC_LOWER_BASE_SHIFT 12
+#define GLPCI_RC_LOWER_EN_SET (1<<8)
+#define GLPCI_RC_LOWER_PF_SET (1<<5)
+#define GLPCI_RC_LOWER_WC_SET (1<<4)
+#define GLPCI_RC_LOWER_WP_SET (1<<2)
+#define GLPCI_RC_LOWER_CD_SET (1<<0)
+
+#define GLPCI_ExtMSR (MSR_PCI + 0x201E)
+#define GLPCI_SPARE (MSR_PCI + 0x201F)
+#define GLPCI_SPARE_LOWER_AILTO_SET (1<<6)
+#define GLPCI_SPARE_LOWER_PPD_SET (1<<5)
+#define GLPCI_SPARE_LOWER_PPC_SET (1<<4)
+#define GLPCI_SPARE_LOWER_MPC_SET (1<<3)
+#define GLPCI_SPARE_LOWER_MME_SET (1<<2)
+#define GLPCI_SPARE_LOWER_NSE_SET (1<<1)
+#define GLPCI_SPARE_LOWER_SUPO_SET (1<<0)
+
+/* VIP GLIU1 port 5*/
+#define VIP_GLD_MSR_CAP (MSR_VIP + 0x2000)
+#define VIP_GLD_MSR_CONFIG (MSR_VIP + 0x2001)
+#define VIP_GLD_MSR_PM (MSR_VIP + 0x2004)
+#define VIP_BIST (MSR_VIP + 0x2005)
+/* AES GLIU1 port 6*/
+#define AES_GLD_MSR_CAP (MSR_AES + 0x2000)
+#define AES_GLD_MSR_CONFIG (MSR_AES + 0x2001)
+#define AES_GLD_MSR_PM (MSR_AES + 0x2004)
+#define AES_CONTROL (MSR_AES + 0x2006)
+/* from MC spec */
+#define MIN_MOD_BANKS 1
+#define MAX_MOD_BANKS 2
+#define MIN_DEV_BANKS 2
+#define MAX_DEV_BANKS 4
+#define MAX_COL_ADDR 17
+/* GLIU typedefs */
+#define BM 1 /* Base Mask - map power of 2 size aligned region */
+#define BMO 2 /* BM with an offset */
+#define R 3 /* Range - 4k range minimum */
+#define RO 4 /* R with offset */
+#define SC 5 /* Swiss 0xCeese - maps a 256K region in to 16K 0xcunks. Set W/R */
+#define BMIO 6 /* Base Mask IO */
+#define SCIO 7 /* Swiss 0xCeese IO */
+#define SC_SHADOW 8 /* Special marker for Shadow SC descriptors so setShadow proc is independant of CPU */
+#define R_SYSMEM 9 /* Special marker for SYSMEM R descriptors so GLIUInit proc is independant of CPU */
+#define BMO_SMM 10 /* Specail marker for SMM */
+#define BM_SMM 11 /* Specail marker for SMM */
+#define BMO_DMM 12 /* Specail marker for DMM */
+#define BM_DMM 13 /* Specail marker for DMM */
+#define RO_FB 14 /* special for Frame buffer. */
+#define R_FB 15 /* special for FB. */
+#define OTHER 0x0FE /* Special marker for other */
+#define GL_END 0x0FF /* end */
+#define MSR_GL0 (GL1_GLIU0 << 29)
+/* Platform stuff but unlikely to change */
+/* Set up desc addresses from 20 - 3f*/
+/* This is chip specific!*/
+#define MSR_GLIU0_BASE1 (MSR_GLIU0 + 0x20) /* BM */
+#define MSR_GLIU0_BASE2 (MSR_GLIU0 + 0x21) /* BM */
+#define MSR_GLIU0_BASE3 (MSR_GLIU0 + 0x22) /* BM */
+#define MSR_GLIU0_BASE4 (MSR_GLIU0 + 0x23) /* BM */
+#define MSR_GLIU0_BASE5 (MSR_GLIU0 + 0x24) /* BM */
+#define MSR_GLIU0_BASE6 (MSR_GLIU0 + 0x25) /* BM */
+#define GLIU0_P2D_BMO_0 (MSR_GLIU0 + 0x26)
+#define GLIU0_P2D_BMO_1 (MSR_GLIU0 + 0x27)
+#define MSR_GLIU0_SMM (GLIU0_P2D_BMO_0)
+#define MSR_GLIU0_DMM (GLIU0_P2D_BMO_1)
+#define GLIU0_P2D_R (MSR_GLIU0 + 0x28)
+#define MSR_GLIU0_SYSMEM (GLIU0_P2D_R)
+#define GLIU0_P2D_RO_0 (MSR_GLIU0 + 0x29)
+#define GLIU0_P2D_RO_1 (MSR_GLIU0 + 0x2A)
+#define GLIU0_P2D_RO_2 (MSR_GLIU0 + 0x2B)
+#define MSR_GLIU0_SHADOW (MSR_GLIU0 + 0x2C) /* SCO should only be SC */
+#define GLIU0_IOD_BM_0 (MSR_GLIU0 + 0xE0)
+#define GLIU0_IOD_BM_1 (MSR_GLIU0 + 0xE1)
+#define GLIU0_IOD_BM_2 (MSR_GLIU0 + 0xE2)
+#define GLIU0_IOD_SC_0 (MSR_GLIU0 + 0xE3)
+#define GLIU0_IOD_SC_1 (MSR_GLIU0 + 0xE4)
+#define GLIU0_IOD_SC_2 (MSR_GLIU0 + 0xE5)
+#define GLIU0_IOD_SC_3 (MSR_GLIU0 + 0xE6)
+#define GLIU0_IOD_SC_4 (MSR_GLIU0 + 0xE7)
+#define GLIU0_IOD_SC_5 (MSR_GLIU0 + 0xE8)
+#define MSR_GLIU1_BASE1 (MSR_GLIU1 + 0x20) /* BM */
+#define MSR_GLIU1_BASE2 (MSR_GLIU1 + 0x21) /* BM */
+#define MSR_GLIU1_BASE3 (MSR_GLIU1 + 0x22) /* BM */
+#define MSR_GLIU1_BASE4 (MSR_GLIU1 + 0x23) /* BM */
+#define MSR_GLIU1_BASE5 (MSR_GLIU1 + 0x24) /* BM */
+#define MSR_GLIU1_BASE6 (MSR_GLIU1 + 0x25) /* BM */
+#define MSR_GLIU1_BASE7 (MSR_GLIU1 + 0x26) /* BM */
+#define MSR_GLIU1_BASE8 (MSR_GLIU1 + 0x27) /* BM */
+#define MSR_GLIU1_BASE9 (MSR_GLIU1 + 0x28) /* BM */
+#define MSR_GLIU1_BASE10 (MSR_GLIU1 + 0x29) /* BM */
+#define GLIU1_P2D_R_0 (MSR_GLIU1 + 0x2A)
+#define GLIU1_P2D_R_1 (MSR_GLIU1 + 0x2B)
+#define GLIU1_P2D_R_2 (MSR_GLIU1 + 0x2C)
+#define GLIU1_P2D_R_3 (MSR_GLIU1 + 0x2D)
+#define MSR_GLIU1_SHADOW (MSR_GLIU1 + 0x2E)
+#define MSR_GLIU1_SYSMEM (GLIU1_P2D_R_0)
+#define MSR_GLIU1_SMM (MSR_GLIU1_BASE4) /* BM */
+#define MSR_GLIU1_DMM (MSR_GLIU1_BASE5) /* BM */
+#define GLIU1_IOD_BM_0 (MSR_GLIU1 + 0xE0)
+#define GLIU1_IOD_BM_1 (MSR_GLIU1 + 0xE1)
+#define GLIU1_IOD_BM_2 (MSR_GLIU1 + 0xE2)
+#define GLIU1_IOD_SC_0 (MSR_GLIU1 + 0xE3)
+#define GLIU1_IOD_SC_1 (MSR_GLIU1 + 0xE4)
+#define GLIU1_IOD_SC_2 (MSR_GLIU1 + 0xE5)
+#define GLIU1_IOD_SC_3 (MSR_GLIU1 + 0xE6)
+#define MSR_GLIU1_FPU_TRAP (GLIU1_IOD_SC_0) /* FooGlue F0 for FPU */
+/* ------------------------ */
+#define SMM_OFFSET 0x80400000 /* above 2GB */
+#define SMM_SIZE 128 /* changed SMM_SIZE from 256 KB to 128 KB */
+
+/* ------------------------ */
+#define DCACHE_RAM_SIZE 0x08000
+#define DCACHE_RAM_BASE 0xc8000
+
+#endif
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