[LinuxBIOS] 440bx folks: looking for spd data

[roger]

I've taken notes on the following aspects of the Northbridge and am
reading the Intel published SPD pdf now. 

The following is only some clippings of what is said in the main pdf and
the updates concerning DRAM config.  I think I have yet to go through
each DRAM register looking for notes pertaining to "what should be set
before/after SPD".


--
Roger
http://www.eskimo.com/~roger/index.html
Key fingerprint = 8977 A252 2623 F567 70CD 1261 640F C963 1005 1D61

Mon May 14 17:23:51 PDT 2007
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(P 29)

In addition to reserved bits within a register, PAC contains address locations in the configuration space of the
Host-PCI Bridge function that are marked Reserved. PAC responds to accesses to these address locations
by completing the host cycle. Software should not write to reserved configuration locations in the devicespecific
region (above address offset 3Fh).
During a hard reset, PAC sets its internal configuration registers to predetermined default states. The default
state represents the minimum functionality feature set required to successfully bring up the system. Hence, it
does not represent the optimal system configuration. It is the responsibility of the system initialization
software (usually BIOS) to properly determine the DRAM configurations, operating parameters and optional
system features that are applicable, and to program PAC registers accordingly.
NOTE
The 440LX AGPset depends on the atomically of configuration cycles in a 2-way SMP system. Thus,
software (BIOS or OS) must guarantee that in a system with two processors only one processor can
access the configuration space at any time. During system initialization, only the Boot Processor
should be allowed access to configuration space. Additionally, PnP BIOS and EISA configuration
utilities must guarantee that addresses 0CF8h to 0CFFh are allocated as motherboard addresses and
not available as I/O locations.


PCISTS - PCI Status Register (Device 0)
Address Offset 06-07h
(Helpful for debugging PCI-PCI Communication?)

PACCFG-PAC CONFIGURATION REGISTER (DEVICE 0)
Offset: 50-51h
PACCFG is a 16-bit register that is used for indicating the system level configuration

3.3.17. PAM-PROGRAMMABLE ATTRIBUTE MAP REGISTERS (PAM[6:0]) (DEVICE 0)
As an example, consider a BIOS that is implemented on the expansion bus. During the initialization process,
BIOS can be shadowed in main memory to increase the system performance. When a BIOS is copied in
main memory, it should be copied to the same address location. To shadow BIOS, the attributes for that
address range should be set to write only. BIOS is shadowed by first doing a read of that address. This read
is forwarded to the expansion bus. The host then does a write of the same address, which is directed to main
memory. After BIOS is shadowed, the attributes for that memory area are set to read only so that all writes
are forwarded to the expansion bus.

3.3.20. DRAMXC-DRAM EXTENDED CONTROL REGISTER (DEVICE 0)
Address Offset: 6A-6Bh
Default Value: 0000h
Bit 7:5
000 - Normal Mode
001, 010, 011, 100, 101-11x - When in one of these modes, the only SDRAM
operations performed by the PAC are NOP, Pre-charge, MRS or Refresh command.

3.3.23. SMRAM-SYSTEM MANAGEMENT RAM CONTROL REGISTER (DEVICE 0)
Some interesting stuff about locking & resetting things here.  Also something
about helping BIOS initialize SMM Space.


(p91)
4.3.1.1. Configuration Mechanism for DIMMs
PAC DRAM Controller uses the Serial Presence Detect (SPD) mechanism for memory array configuration, as
defined in the JEDEC 168-pin DIMM Standard Specification.
NOTE
It is very difficult to program the 82443LX DRAM Timing Register (Register 58h, Device #0) and the
DRAM Buffer Strength register (Register 6C-6Fh, Device #0) without information garnered using Serial
Presence Detect (SPD). Thus, support for SPD in a PAC memory array is required.
The system BIOS must program the DRAM size, type, timing, and buffer strength registers in the 82443LX. It
gathers this information by the Serial Presence Detect (SPD) mechanism.
DRAM Configuration is performed by the BIOS, which follows these six steps:
1. The system BIOS must loop through the rows of memory (8 rows for Memory Configuration #1, 6 rows for
Memory Configuration #2) reading Serial Presence Detect (SPD) data. This will allow it to determine
whether each DIMM in the array is single or double sided. The system BIOS must also determine the
type of memory contained in each row, and set the DRAM Type registers
accordingly (DRT-Device #0,
Register 55-56h). Also, note that, at this time, system BIOS should determine the SLOWEST CAS
Latency of all of the available SDRAM DIMMs in the array.
2. BIOS must next loop through the rows of memory, initialize and configure each row of SDRAM. Note that
the SDRAM DIMMs will ALL be programmed to either CAS Latency=2 or CAS Latency=3; whichever is
the SLOWEST DIMM found in step 1.
3. BIOS must next loop through the rows of memory, reading SPD data to determine the DRAM size. The
DRB's (DRB[7:0]-device #0, register 60-67h) can now be set. Additionally, several different bytes of
SPD data can be read to determine the timing values to be used when programming the memory timing
register (DRAMT-device #0, register 58h) and to determine if ECC can be enabled (if all available
DIMM's support ECC).
4. BIOS must next program the Memory Buffer Strength Control Register (MBSC-device #0, register
6C-6Fh). To program this register properly, additional bytes of SPD data must be read for each row of
memory.
5. BIOS can use the data found in step 3 to program the DRAM timing register
(DRAMT-device #0,
register 58h).
6. Lastly, if ALL of the DIMM's in the array support ECC, then ECC should be enabled in PAC.


(Stopped Reading of Main Spec p94)







Update Errata

1. Locked Cycle Retry
Problem: The following sequence of events following a locked retry cycle to DRAM may result in system
failure.
UP Scenario:
a) The Intel 440BX AGPset is in the PIIX regime (i.e., PIIX4 has a pending cycle to DRAM).
b) The processor issues a locked read to DRAM which results in a write back.
c) The Intel 440BX AGPset retries the locked cycle to DRAM (due to pending PCI
cycle to DRAM).
d) The Intel 440BX AGPset accepts the write data for the write back cycle and posts it.
e) System fails
DP Scenarios:
Case 1:
a) A PCI master initiated cycle is deferred.
b) The processor issues a locked read to DRAM which results in a write back.
c) The Intel 440BX AGPset retries the locked cycle to DRAM (due to pending PCI
cycle to DRAM).
e) The Intel 440BX AGPset accepts the write data for the write back cycle and posts it.
f) System fails
Case 2:
a) CPU1 performs a locked cycle to DRAM.
b) CPU2 attempts to execute a locked cycle to DRAM which results in a write back.
c) The Intel 440BX AGPset retries the cycle from CPU2.
d) The Intel 440BX AGPset accepts the write data for the write back cycle and posts it.
e) System fails
Implication: System failure may occur.
Workaround: UP workaround - Set PCI Configuration Register 0F4h, bit 5 to 1. This will force the BX to
continuously assert BPRI# when there is a pending cycle from the PIIX to DRAM
DP workaround Assert BNR# whenever LOCK# is asserted
Status: This erratum is intended to be fixed in the next stepping of the 82443BX.



Specification Clarification

1. Normal Refresh Enable
When the user performs a soft reset, the PIIX will drive SUSTAT# to BX. This will force the BX
to switch to a suspend refresh state. When the BIOS attempts to execute cycles to DRAM, the BX
will not accept these cycles because it believes that it is in a suspend state
After coming out of reset the software must set the normal refresh enable bit (bit 4, power
management control register Offset 7Ah) in the 82443BX before doing an access to memory.

6. Modifying DRAM Configuration Registers during DRAM Cycles
Modifying any configuration registers that affect DRAM (SDRAM or EDO) while DRAM cycles
are running may cause system problems. The DRAM configuration registers should be completely
initialized before running DRAM cycles.




Update Errate

5. SDRAM Leadoff Command Timing Must Be Set to Four CPU Clocks
Issue: Timing issues exist when the Leadoff Command Timing (LCT) bit, bit 3 in
the SDRAM Control Register (Device 0, Function 0, Register 76-77h), is
programmed to a '1.' This corresponds to a CS# leadoff time of three CPU clocks.
Implication: A CS# leadoff time of 3 is not allowed.
Workaround: Program the LCT bit to '0', which corresponds to a CS# leadoff time of four CPU clocks.
Status: Fixed in B-0 stepping.

9. C3/POS/STR Memory Hang Condition
Issue: SDRAM may be prevented from being put into self-refresh state when a self-refresh entry request triggered by SUS_STAT# assertion collides with a normal refresh caused by internal timer expiration.
Implication: The system may hang if an unsuccessful self refresh entry sequence occurs.
Workaround: Please refer to the SDRAM Suspend Refresh Erratum APM Workaround Write-up, Rev 1.0 for a software workaround solution.
Status: Fixed in B-0 stepping.