[LinuxBIOS] GA-M57SLI-S4 dual bios pins was Re: New with a GA-M57SLI-S4

[Peter Stuge]

Hi,

On Thu, Mar 29, 2007 at 12:23:12AM +0200, ST wrote:
> Hi Peter, Stefan, Corey, Jose
> > Chip pin = (37-yourpin) mod 32
> Unfortunately i counted clockwise while the std pin numeration is
> counter-clockwise. This makes the pinsfunctions somehow weird and
> your work unfortunately moot...

I hate to be a besserwisser, but I did take into account you
numbering the pins clockwise. The simple formula should be
correct except for pin 32, when it returns 0. :p


> but you managed to motivate me to take a closer look :-).

Excellent! The more eyes the better.


> Bios Pins       connected to			True Pin(tm)
[..]

A comment on the pin names. This chip supports three usage modes;
A/A Mux, LPC and FWH.

A/A Mux is used for factory programming of unconnected flash chips.
It's a parallell mode allowing fast flashing.

LPC is Low Pin Count, which is what is used on this board.

FWH is Firmware Hub, which is just like LPC but with a few extras,
most notably the ID0-ID3 signals which would distinguish several
chips otherwise connected in parallell.


> So according to my great connection list VCC is connected to GND.
> Ouch, who has designed this MB 8-). Oh wait... Jose could you do
> me a favor and recheck these lines with error?

WP_BIOS_2 is definately GND considering the kind of input WP_BIOS_1
is connected to and the other places that connect to WP_BIOS_2.

The only confusion comes from pin 25 which should be Vcc, but the
connection to GND could (and surely does) have an explanation.


> (Btw. our listing of the not connected pins is identical to mine).
> Especially the T1 or T2 pin and WP_BIOS connections.
> 
> > TBL is top boot block protection. 
> This doesn't seem to connect to any of the jumpers.

No.


> > Also, what are T22 and T12?
> Please see: 
> http://private.vlsi.informatik.tu-darmstadt.de/st/dual_bios_GA-m57SLI-S4.jpg

Thanks! Good picture.

BIOS_WP is write protection.

Shorting 1-2 on PCI_BT would pull LFRAME low on both chips,
effectively disabling them, supporting the suggestion that booting
from the PCI bus would be allowed. (But more hardware has to be
involved to make it happen, possibly included in the chipset,
possibly componentes not populated on the final boards.)


> These are open pins which might be transistors but are only Three
> open pins each. Between the PCIex1 sockets and the flash chips.

They could be transistors or diodes. Hard to tell..

But it's nice to have some pads to solder on! :)


> > > T13,T23 and WP_BIOS_2 are connected.
> Theres some error in there. I'm not sure. But WP# is active low so,
> at least WP_BIOS_2 should be GND or s.t. like that?

Sure. T1-3 and T2-3 are GND. The wider traces also support that
suggestion.


> > All pins/pads you marked with ? are either N/C (not connected)
> > or RES (reserverd) on the chip and can be ignored for booting
> > purposes.
[..]
> I think they are all pulled to ground. Which leaves us with no
> unknown pins for both sockets?

None of them are relevant for LPC.


> Open questions:
> * How can writing to only one chip be realized?

Not just writing, but using. If we learn how pin 24 INIT# is
controlled on both of the chips we may be able to create a
simple BIOS savior circuit on the mainboard itself.

INIT# is the only relevant signal that isn't connected straight
across.


> * Are these lower open pads above Q4 and R102 really not connected?
> Somehow i think these should be the transistors for controlling the
> write pins of these chips.

I'm not sure.

It seems Q4-2 is connected to pin 2 RST# - could you verify that?

I would guess Q4-3 is connected to GND.

Is the left pad of R89 in the picture (the one nearest T2 with a wide
trace that runs into the Q4 outline) connected to Vcc or GND?

Use e.g. chip pin 32 for Vcc.


//Peter