[LinuxBIOS] VT8605 RAM controller init

Stefan Reinauer stepan at coresystems.de
Sun Mar 25 04:46:16 CEST 2007

* sanjay tiwary <stiwary20 at yahoo.com> [070324 19:49]:
>     2. Now i would like to ask couple of question. Since raminit does
> not complain any failure and ramcheck also passes ramtest.Next, code
> in crt0.S is able to copy the code from ROM to RAM. I am also able to
> read the code and print them in the serial output.So my question is,
> if i am able to read/write correct data to/from RAM, why is there
> doubt on incorrect DRAM initialisation?

because you can not jump to ram. And because of your register dump shows
it. You did at least not set the following registers correctly. (Lots
more, but these are DRAM controller specific)

* 0x50-55 (Phase Control, Defer Timer, Misc, Cacheable regions)
* bank0 dram row ending address is wrong (0x5a)
* dram arbitration control (0x6b)
* dram arbitration timer (0xf8, 0xf9)

> If i am not able to jump to a designated place (0x4000) in RAM simply
> due incorrect DRAM initialisation, then what are those things which i
> am not taking care of during DRAM initialization? Can u pls hightlight
> those area in RAMINIT so that i can re-walk those area.

No idea what is actually wrong in your code. Some wrong/missing bits can
be deduced from the pci config space dumps you sent. More details would
require looking at the code or using a crystal ball.  ;-)

>  3. if really, the DRAM initialization is correct, then what are the
>  factors that may stop/misdirect the control to jump to a correct
>  location in RAM.  I tried to print the contents from the RAM which is
>  copied from the ROM to RAM in the start of crt0.S, they are byte by
>  byte same as is for c_start.o
The same jump works on 50 other mainboards. It is highly unlikely that a
bug is revealed here. (sorry if I sound monotonous)
> 6. i have compared the register dump for linuxbios and legacy bios.They are not
> exactly same. Should i try to cpmpare the entire dump or the register dump of
> device 00.0 only? 
Only those of the DRAM controller. consult your VIA PM133 data sheet for
details on which devices need to be touched for DRAM init. Most likely
it is 0:0.0 though.

You're not that far off,... start with comparing 0:0.0  registers with
the data sheet and see how far it gets you


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