[LinuxBIOS] [PATCH] Add initial serial output for Via vt82c686

Corey Osgood corey_osgood at verizon.net
Wed Mar 14 06:52:06 CET 2007

Uwe Hermann wrote:
> OK, I tried this code today on an MSI K7T Turbo (MS-6330), which uses
> the VT82C686B southbridge.
> I didn't manage to get serial output with this code, yet. I verified
> that I can boot Linux with the proprietary BIOS and that I can use
> minicom for serial connections to another PC (COM1, 115200 bps, 8N1).

I think this may be your problem, although gcc should have corrected it
or else given an error:

> -
> -        w83627hf_enable_serial(SERIAL_DEV, TTYS0_BASE);
> +        vt686_enable_serial(SERIAL_DEV, TTYS0_BASE);

this should be vt686_enable_serial();, where it's built into the
southbridge, its location is static afaik.

> Attached is my quick hack which I used in addition to your patch to be
> able to build an image. I abused the tyan/s2735, but it really doesn't
> matter which board you use in this case (I think)...
> In targets/tyan/s2735/Config.lb I added
>   option ROM_SIZE = 256*1024
> and set the payload to
>   payload /etc/hosts
> for a dummy payload (doesn't matter yet).
> Maybe I'm missing some important detail in my code? Can you please post
> your full patch you use for building an image?

At the moment, my desktop, with all of my linuxbios stuff on it, is in
the middle of a dist-upgrade, with no end in sight (the joys of using
ubuntu 7.04 beta), and I'm headed to bed. I'll post my patch tomorrow
afternoon. I also used tyan s2735 as a base, is it possible that LB is
looking for the P4 cpus and not handling the k7? Or does that happen
after early serial?

Aside from that, it was just tiny changes, like removing all the
mptable/pirq table stuff, and a few other things in Options.lb that were
specific to that board, such as changing over to socket 370 cpus and my
northbridge (which is a work in progress, and isn't important). I also
changed Config.lb in the targets directory to only make a fallback
image, adjusted the fallback image size accordingly, and changed
failover.c in the src/mainboard directory to only boot the fallback image.

>> Index: src/southbridge/via/vt686/vt686_early_serial.c
>> ===================================================================
>> --- src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
>> +++ src/southbridge/via/vt686/vt686_early_serial.c	(revision 0)
> I've been thinking about the name and location of this code. I think
> it's better to name the directory vt82c686 (no "a" and no "b") and use it
> for both variants (a/b).
> Please rename all respective variable names and file names to vt82c686*.

Again, I'll handle this later. I assume you'd like VT82C694X (when it's
done) to have the full name also? Or perhaps even vt82c69xx, since it
should also work fine with vt82c693a (although I'd have to review the
docs some more before I'd do this).

> I guess we can keep the code in src/southbridge/via for now (instead of
> src/superio/via), I'm still undecided which is better here, but
> we can always move the code later...

If it does get moved, then via vt8231 and vt8235 should also have their
super i/o functions moved, to avoid confusion and keep consistent.
Frankly, the way I see it, the super i/o is just another function of the
southbridge, and the super i/o code will nearly *always* be used along
with the southbridge, and *never, ever* be used by itself, so why
scatter it around?

>> +/* Enable the peripheral devices on the VT686 Super I/O chip. */
>> +static void vt686_enable_serial( void )
>> +{
>> +	/* (1) Enter the configuration state. ( Set PCI Function 0 Rx85[1] = 1 ) */
>> +	device_t dev;
>> +	/* First, find the southbridge. Trip the POST card if we don't (does die() do this?)*/
>> +	dev = pci_locate_device( PCI_ID( PCI_VENDOR_ID_VIA, PCI_DEVICE_ID_VIA_82C686 ), 0 );
>> +	if ( dev == PCI_DEV_INVALID ) {
>> +		outb( 0xff, 0x80 );
>> +		die( "Southbridge not found\r\n" );
>> +	}
> First I suspected that this code might not work for my board, but the
> PCI IDs are ok:
> 00:07.0 0601: 1106:0686 (rev 40)
> I don't have a working POST card at the moment, unfortunately (my old
> one is broken), so I cannot verify much here...

At line 95 (or around there), try changing it to this, if it still
doesn't work after the above fix:

if ( dev == PCI_DEV_INVALID ) {
	dev = PCI_DEV(0, 7, 0);

I'd say keep the post code too, but without a post card that's
pointless. Finding the southbridge and writing to that register is
essential, if that doesn't happen you're just writing to the read-only
floppy status port, if you don't die(). Perhaps it would be possible to
send a beep or flash a light if the southbridge isn't found, I'll look
into that.

>> +	pci_write_config8( dev, 0x85, 0x1f ); //Enable the SuperI/O, SI/O Config, and disable everything else
>> +	
>> +	/* 2) Configure the chip */
>> +	vt686_sio_write( VT686_POWER, 0x00 ); //Make sure all devs are powered on. FIXME: only power on used devices
>> +	vt686_sio_write( VT686_COM_CFG, 0x00 ); //Set up COMs for normal (non-IR) operation
>> +	vt686_sio_write( VT686_FS, 0x07 ); //Disable Floppy, Enable COM1, Disable COM2 and Parallel Port
> This part should check whether COM1 or COM2 was selected by the user,
> then only enable that one. No other devices yet (this is
> vt686_early_serial.c so we only need serial).

For now, I'll just use a #define at the start of the file to set up COM2
instead of COM1, and clean it up later. For the moment, my real focus is
basic setup of the northbridge (which seems to be partially working, but
still failing ram tests), then smbus, and the rest of the chipset
functions, then I can go back and make it all look nice and fully
functional and use Options.lb's defines wherever possible. I plan on
modifying this some before I'm finished, but I figured I'd submit a
patch for it now, since I know there was one email a while back asking
about this chipset.


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