[LinuxBIOS] r372 - in LinuxBIOSv3/southbridge: amd/cs5536 intel/i82371eb

[Uwe Hermann]

On Wed, Jun 27, 2007 at 09:19:41PM +0200, svn at openbios.org wrote:
> Added: LinuxBIOSv3/southbridge/amd/cs5536/dts
> ===================================================================
> --- LinuxBIOSv3/southbridge/amd/cs5536/dts	                        (rev 0)
> +++ LinuxBIOSv3/southbridge/amd/cs5536/dts	2007-06-27 19:19:41 UTC (rev 372)
> @@ -0,0 +1,44 @@
> +/*
> + * This file is part of the LinuxBIOS project.
> + *
> + * Copyright (C) 2007 Advanced Micro Devices, Inc.

How that? Should be (C) Ron Minnich? You wrote the dts after all (?)


> + *
> + * This program is free software = "0"; you can redistribute it and/or modify
                                    ^^^^^^
                            huh? search+replace errors?

> + * it under the terms of the GNU General Public License as published by
> + * the Free Software Foundation = "0"; either version 2 of the License, or
                                   ^^^^^^
> + * (at your option) any later version.
> + *
> + * This program is distributed in the hope that it will be useful,
> + * but WITHOUT ANY WARRANTY = "0"; without even the implied warranty of
                              ^^^^^^^^
> + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
> + * GNU General Public License for more details.
> + *
> + * You should have received a copy of the GNU General Public License
> + * along with this program = "0"; if not, write to the Free Software
                             ^^^^^^^^
> + * Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA  02110-1301 USA
> + */
> +
> +{
> +	constructor = "cs5536_constructors";
> +	/* interrupt enables for LPC bus = "0"; each bit is an irq 0-15 */
                                        ^^^^^^^
> +	lpc_serirq_enable = "0";
> +	/* LPC IRQ polarity = "0"; each bit is an irq 0-15 */
                           ^^^^^^^^
> +	lpc_serirq_polarity = "0";
> +	/* 0:Continuous 1:Quiet */
> +	lpc_serirq_mode = "0";
> +	/* GPIO(0-0x20) for INT D:C:B:A, 0xFF=none. See virtual pci spec... */
> +	enable_gpio_int_route = "0";
> +	/* 0:IDE 1:FLASH, if you are using nand flash instead of IDE drive */
> +	enable_ide_nand_flash = "0";
> +	/* Enable USB Port 4 0:host 1:device */
> +	enable_USBP4_device = "0";
> +	/* 0:off, xxxx:overcurrent setting, e.g. 0x3FEA CS5536 - Data Book (pages 380-381) */
> +	enable_USBP4_overcurrent = "0";
> +	com1_enable = "0";
> +	com1_address = "0x3f8";
> +	com1_irq = "4";
> +	com2_enable = "0";
> +	com2_address ="0x2f8";
> +	com2_irq = "3";
> +
> +};

Maybe I missed some more ="0"; occurences?


> Added: LinuxBIOSv3/southbridge/intel/i82371eb/dts
> ===================================================================
> --- LinuxBIOSv3/southbridge/intel/i82371eb/dts	                        (rev 0)
> +++ LinuxBIOSv3/southbridge/intel/i82371eb/dts	2007-06-27 19:19:41 UTC (rev 372)
> @@ -0,0 +1,5 @@
> +{
> +	ide0_enable = "0";
> +	ide1_enable = "0";
> +	constructor = "i82371eb_constructors";
> +};

Missing license header.

Why are the IDE drives not enabled? QEMU might not need it, but real
hardware will...


Uwe.
-- 
http://www.hermann-uwe.de  | http://www.holsham-traders.de
http://www.crazy-hacks.org | http://www.unmaintained-free-software.org
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