[LinuxBIOS] rom-madness: CFI vs FWH vs SPI, 5V, 3.3, ...

Tom Sylla tsylla at gmail.com
Tue Apr 10 14:44:48 CEST 2007

A good overview; some corrections and comments in-line:

Peter Stuge wrote:
> Parallel flash found in PCs uses 5V signalling. As Segher pointed
> out, early flash chips required a special programming voltage around
> 12V for erasing and programming, but after a while reprogramming
> became possible with a single voltage supply.

3V parallel flash was also common just before LPC took over. e.g., 
SST29LE020 in both DIP and PLCC was used a lot of places.

> Then, there's the LPC bus, Low Pin Count Interface. LPC is a five pin
> bus, four combined address/data lines and one clock. There's also a
> handful optional sync and control signals for better reliability.

Minimal LPC is 7 wires: CLK, LAD[3..0], FRAME, RESET. The optional 
signals are not for reliability, they are for more functionality: SERIRQ 
and DRQ for interrupt and legacy DMA support; PME and CLKRUN for power 

> LPC does not mandate a single electrical signalling environment,
> instead it refers to the PCI signalling used in the system. If system
> PCI uses 5V then LPC devices must handle 5V. If system PCI uses 3.3V
> then LPC devices must work with 3.3V. LPC chips come in 32-pin PLCC
> packages. 3.3V LPC devices may break if put in a 5V parallel socket.
> 5V LPC flash is not common.

TSSOP LPC and FWH flash are also common. (lower profile for embedded 
platforms, etc.)

The voltage signalling stuff is not correct. The LAD[3:0] / LFRAME# / 
LDRQ# / SERIRQ / LPME# signals are *defined* to use 3.3V PCI signalling. 
 From the LPC spec:

'The AC and DC specifications for these signals are identical to those 
defined in Section 4.2.2 of the "PCI Local Bus Specification, Rev 2.3". 
That section contains the specifications for the 3.3V PCI signaling 

LRESET# / LCLK / CLKRUN# fit your description (matching the platform PCI 
signalling requirements, basically, those signals should be 5V tolerant 
if used in a system where those signals run at 5V)

Also, have you ever seen a 5V-powered LPC or FWH ROM? I don't think they 
ever existed.

> FWH, Firmware Hub, is an LPC flash ROM with some extra functionality
> like a couple of GPIO signals and also a few pins for arbitration
> between several FWH chips on the same LPC bus.

Many "normal" LPC ROMs have the arbitration signals, too. The real 
important difference between a FWH and regular LPC ROM is that the FWH 
ROMs support the "Firmware Memory cycles". Normal LPC memory cycles only 
transfer one byte at a time. FWH memory cycles can do 1, 2, 4, 16, or 
128 bytes per transfer if both sides support it. (this cuts down on the 
overhead per byte of ROM fetch)

> SPI, Serial Peripheral Interface, is a four-wire bus (chip select,
> serial in, serial out and clock) that is becoming popular because
> memory devices can be made smaller, with fewer pins, which allows
> more space for other chips on the board. SPI chips are usually in
> 8-pin SOIC (about 1x1 cm, a couple of mm high, pins on two opposite
> sides) packages and those found on PC mainboards so far have been
> using 3.3V signals, but SPI also does not mandate a single electrical
> signalling environment.

Just a note: SPI ROMs are also growing in popularity because they 
additionally have large markets for MCUs and FPGAs, which drives their 
costs down.

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