[LinuxBIOS] rom-madness: CFI vs FWH vs SPI, 5V, 3.3, ...

Peter Stuge stuge-linuxbios at cdy.org
Tue Apr 10 08:08:41 CEST 2007

On Tue, Apr 10, 2007 at 03:54:22AM +0200, Luc Verhaegen wrote:
> I asked about the 3.3V vs 5V roms, and i only got further confusion...

I'll go chronologically.

First, there's parallel flash. Parallel flash on PC mainboards has an
address bus which is between 17 and 19 bits wide and a data bus which
is 8 bits wide. Naturally many flash chips can be combined with glue
logic if a larger address bus is required but I haven't seen that
since 286:s.

Parallel flash typically comes in 32 pin DIP (rectangular, pins along
both longer sides), PLCC (nearly square, pins on all four sides) or
32, 40 or 44 pin TSOP (about 1mm thick, rectangular, pins along both
shorter sides) packages.

Parallel flash found in PCs uses 5V signalling. As Segher pointed
out, early flash chips required a special programming voltage around
12V for erasing and programming, but after a while reprogramming
became possible with a single voltage supply.

Then, there's the LPC bus, Low Pin Count Interface. LPC is a five pin
bus, four combined address/data lines and one clock. There's also a
handful optional sync and control signals for better reliability.

LPC does not mandate a single electrical signalling environment,
instead it refers to the PCI signalling used in the system. If system
PCI uses 5V then LPC devices must handle 5V. If system PCI uses 3.3V
then LPC devices must work with 3.3V. LPC chips come in 32-pin PLCC
packages. 3.3V LPC devices may break if put in a 5V parallel socket.
5V LPC flash is not common.

FWH, Firmware Hub, is an LPC flash ROM with some extra functionality
like a couple of GPIO signals and also a few pins for arbitration
between several FWH chips on the same LPC bus.

So far, flash has been programmed the same way, using a protocol
standardized by JEDEC, short for the Joint Electronic Device
Engineering Council.

Any flash chip data sheet documents the commands. One thing to note
is that in order to do anything but read data from the memory (ie.
identify the particular chip, erase it or program it) writes need to
be made to the chip. A data protection scheme requires certain data
to be written to certain addresses in different patterns depending on
the desired operation.

SPI, Serial Peripheral Interface, is a four-wire bus (chip select,
serial in, serial out and clock) that is becoming popular because
memory devices can be made smaller, with fewer pins, which allows
more space for other chips on the board. SPI chips are usually in
8-pin SOIC (about 1x1 cm, a couple of mm high, pins on two opposite
sides) packages and those found on PC mainboards so far have been
using 3.3V signals, but SPI also does not mandate a single electrical
signalling environment.

SPI chips use a different command set, but the principles are still
the same, there are commands for block erase, chip erase, byte
program and identification. SPI being serial also has a stream
program mode where only one command needs to be sent to the device
followed by a large stream of data that should be written to memory.

All flash needs to be erased before programmed. Erased flash has all
bits set. Programming flash entails flipping bits to 0 at appropriate
places. Bits can not be flipped back to 1 individually, only by erase

Flash has different page sizes. Flash can have boot block protection
requiring special action to be taken in order to erase the top or
bottom pages.

These reprogramming parameters depend on the device ID, which as
mentioned earlier can only be read from the device when writes to the
chip are working.

CFI is the Common Flash Interface as developed by Intel and friends
and published by Intel.

CFI amounts to storing the parameters themselves in the flash chip,
rather than just a device ID. This way, software written for CFI will
be future proof and not need upgrading any time a new device ID is
put on the market.

CFI covers both 8-bit wide and 16-bit wide flash.


More information about the coreboot mailing list