[LinuxBIOS] DK8-HTX FILO IDE timeout
Lu, Yinghai
yinghai.lu at amd.com
Fri Sep 22 00:28:44 CEST 2006
Check serengeti_leopard or tyan/s2881 etc MB Config.lb to add two lines
to enable your IDE devices.
YH
-----Original Message-----
From: Chris Stillo [mailto:cstillo at comcast.net]
Sent: Thursday, September 21, 2006 3:24 PM
To: Lu, Yinghai
Cc: linuxbios at linuxbios.org; Stefan Reinauer
Subject: Re: [LinuxBIOS] DK8-HTX FILO IDE timeout
No, those lines are not there in MB Config... I serach for 'ide0' and
find nothing... where exactly do they go in the file?
> Please check if you have register "ide0_enable"="1" in MB Config.lb
>
> chip southbridge/amd/amd8111
> # this "device pci 0.0" is the parent the next one
> # PCI bridge
> device pci 0.0 on
> device pci 0.0 on end
> device pci 0.1 on end
> device pci 0.2 on end
> device pci 1.0 off end
> end
> .....
> register "ide0_enable"="1"
> register "ide1_enable"="1"
>
> ....
>
>
> YH
>
>
> -----Original Message-----
> From: Chris Stillo [mailto:cstillo at comcast.net]
> Sent: Thursday, September 21, 2006 3:13 PM
> To: Lu, Yinghai
> Cc: linuxbios at linuxbios.org; Stefan Reinauer
> Subject: Re: [LinuxBIOS] DK8-HTX FILO IDE timeout
>
> Hi YH,
>
> I checked MB Config.lb as you suggested. From lspci I know my IDE
> controller is here:
>
> 00:07.1 IDE interface: Advanced Micro Devices [AMD] AMD-8111 IDE (rev
> 03)
>
> Yet I do not see 00:07.1 mentioned in the MB Config.lb in the
> southbridge section. Maybe this is the issue... , maybe IDE is not
> configured since SATA would be mostly used? (My SATA drive is
> recognized, but has XP on it :| -- it is presenlty disconnected).
>
> I also included AMD 3111 chip.h below, which looks ok. I have not
> modified either file at all.
> If you see an error please let me know...
>
> Thanks,
> Chris
>
>
>
>> Check your MB Config.lb to see if amd8111 is under correct 0.18.0
>>
> link.
>
>>
>>
> # config for Iwill/DK8HTX
> chip northbridge/amd/amdk8/root_complex
> device pci_domain 0 on
> chip northbridge/amd/amdk8
> device pci 18.0 on # LDT 0
> chip southbridge/amd/amd8131
> device pci 0.0 on end
> device pci 0.1 on end
> device pci 1.0 on end
> device pci 1.1 on end
> end
> chip southbridge/amd/amd8111
> # this "device pci 0.0" is the parent the next one
> # PCI bridge
> device pci 0.0 on
> device pci 0.0 on end
> device pci 0.1 on end
> device pci 0.2 on end
> device pci 1.0 off end
> end
>
------------------------------------------------------------------------
> -------------------------------
>
> /LinuxBIOSv2/src/southbridge/amd/amd8111
> bash-3.1$ more chip.h
>
> #ifndef AMD8111_CHIP_H
> #define AMD8111_CHIP_H
>
> struct southbridge_amd_amd8111_config
> {
> unsigned int ide0_enable : 1;
> unsigned int ide1_enable : 1;
> unsigned int phy_lowreset : 1;
> };
>
> struct chip_operations;
> extern struct chip_operations southbridge_amd_amd8111_ops;
>
> #endif /* AMD8111_CHIP_H */
>
>
>> YH
>>
>>
>>
>>
>>
>
>
>
>
>
>
>
>
More information about the coreboot
mailing list