[LinuxBIOS] MB1030 / 3036 VGA resume
chris at suehsi.de
Mon May 8 21:21:07 CEST 2006
Peter Stuge schrieb:
> On Mon, May 08, 2006 at 07:27:07PM +0200, Christian Sühs wrote:
>>Can somebody have a look to the gx1 datasheet on page 42 - 50.
>>I'm not sure, but CR0 (Control Register 0) is set to 60000010h
>>after a hardware reset.
>>That means, that the 16K L1 Cache is disabled !?
>>I can't see any code in LB which enables L1 cache on cpu init.
>>Could somebody compare this.
> --8<-- include/cpu/x86/cache.h
> static inline void enable_cache(void)
> unsigned long cr0;
> cr0 = read_cr0();
> cr0 &= 0x9fffffff;
Well, I have seen that code, but what about the registers.
Is cache enabling a standard x86 prozedur?
> --8<-- cpu/amd/model_gx1/Config.lb
> dir /cpu/x86/cache
> driver model_gx1_init.o
> --8<-- Message-ID: <43A551D8.5060208 at suehsi.de> (Dec 2005)
> Initializing CPU #0
> CPU: vendor Centaur device 698
> Enabling cache
That is my epia M Board ;)
Currently we talk about MB3036 from Allwell.
> That email is the only one I found from you to the list where
> Enabling cache occurs. Check your serial output to see if it's still
> there, as it should be.
Ok, I will have a look.
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