[LinuxBIOS] USB Host to Host Debug Dongle/Cable

Richard Smith smithbone at gmail.com
Sun Jul 23 18:23:57 CEST 2006

On 7/23/06, Stefan Reinauer <stepan at coresystems.de> wrote:
> * Richard Smith <smithbone at gmail.com> [060723 04:15]:
> > I see having the target send control packets with the serial bytes in
> > them.  Are any of our debug prints greater than say 50 characters or
> > so?  Max control packet is 64 bytes and both sides must support that
> > since they are hosts.
> Wait., USB2 Debug Mode has a maximum packet size of 8 bytes (64 _bits_)
> Which is why it does not need RAM to operate:

I should have clarified.  I was discounting the debug port (because
its optional) until its shown that its a common feature on 2.0

Neither of the the bridges on my laptop (NEC) or my desktop (VIA) show
a debug implementation.

> > I see having the target just spit OUTs with the debug data in them.
> Do you have a sample implementation?

No.. Its just a guess from the work I've done with my embedded USB
stack I have on another product.  The interface there is _much_
simpler all I have is a data FIFO and a few bits to tell me its done.
If I stuff data into the FIFO and hit write then out it goes.

I was looking at the specs to see what it would take to do something
similar with a (OUE)HCI but I stopped going much further when I saw
that I would need working RAM.

> Yes, this would definitely be the preferred method. The question is:
> Does the end point really have to be in a special mode (debug mode as
> well?)

I was thinking you  might need to bypass some of the timeouts and such.

> The problem as far as I can tell is that JTAG needs an extensive per
> system adaption on the client side that is usually only available for
> windows. Benefit is that we can single step, reflash and read memory and
> a console with the same cable for less than 100$ (the software is where
> the money is here.

> The de facto standard open source tools are available here:
> http://openwince.sourceforge.net/jtag/

They still work though.  I have a parallel port wiggler interface
thats a copy of an Altera byteblaster.  I had to make a small patch
(posted to OLPC) to fix up the compile but after that I was able to
dump a scan chain on one of my Altera boards just fine.

Not that that helps much.  Since like you said all the magic is in
knowing what to send down to the part.

Richard A. Smith

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