[LinuxBIOS] USB Host to Host Debug Dongle/Cable

Peter Stuge stuge-linuxbios at cdy.org
Sun Jul 23 07:54:32 CEST 2006

On Sat, Jul 22, 2006 at 09:15:02PM -0500, Richard Smith wrote:
> What concerns me is a topic that Stefan already brought up. 
> Talking to the USB bridge on the target.  AFAICT you have to have
> ram working to use an [OUE]HCI controller.  You set up the base
> address on a 4k RAM boundary, then the frame counter, then stuff
> the data your want to send in ram and hit the go bit.

Isn't the PCI register space and BAR contents decoded by the EHCI
controller to hardware registers?

"Only" PCI bus access is required for the EHCI debug mode if I
understand correctly, I don't even think it has to be completely
configured on the PCI bus. Appendix C of the EHCI 1.0 spec covers
the debug port.

While it seems that the connected device must be a Debug Class device
it would be quite possible to make a device compliant with the Debug
Class spec only on the target side and then have a regular serial
port on the other (host/remote) end.

I think a simple-as-possible circuit for a USB2 high-speed device
with a serial port is all that is needed.

Note that the debug port is an optional implementation feature of the
EHCI spec. Intel ICH6 implements it. Check your system with:

# lspci -vs $(lspci|grep EHCI|cut -f1 -d' ')
00:1d.7 USB Controller: Intel Corporation 82801FB/FBM/FR/FW/FRW (ICH6
Family) USB2 EHCI Controller (rev 03) (prog-if 20 [EHCI])
        Subsystem: IBM Unknown device 0566
        Flags: bus master, medium devsel, latency 0, IRQ 5
        Memory at b0000000 (32-bit, non-prefetchable) [size=1K]
        Capabilities: [50] Power Management version 2
        Capabilities: [58] Debug port

The last line is the winner.

I just added a EHCI Debug Port wiki page to collect whatever we come
up with in this thread, and primed it with some of this info.


More information about the coreboot mailing list