[LinuxBIOS] SPD as debug channel

Segher Boessenkool segher at kernel.crashing.org
Fri Dec 1 23:31:48 CET 2006

>> The assumption was that not much needs to happen before the SPD I2C
>> bus is accessible by the CPU - is that valid?
> Since you need I2C, you need to get parts of the south bridge working.
> So, its basically the same amount of work as with the USB debug port.

Most systems I work with have I2C controllers (and typically
more than one) in the north bridge, not somewhere south (which
is an insane idea).

> Question is: Will we see systems without USB (debug port) but with  
> DDR2
> sockets?

Yes.  They exist already (mostly in the embedded world, of

>> If not, what IS easily accessible besides the boot ROM? (Which we
>> don't want to rely on since we don't know exactly what it will speak
>> when in the future.) We just need one bit that can do kHz signalling.
>> SMI#?
> Boot rom is a good start I bet. That will always be there (as long  
> as we
> all do firmware development at least).
> It might be parallel yesterday, LPC today and SPI tomorrow, but that
> is only the interface it connects to. Different connector, different
> VHDL source and we should be fine, no?

SPI buses as implemented on most x86 systems for flash, do _not_
support attaching extra devices on the bus (you'd need a separate
chip-select signal, and those either don't exist or aren't readily
available on the board).

> If LPC goes away, we need to do SPI. Ok. If we get DDR3, we would have
> to do that. Technical standards come and go,.. I'd prefer a solution
> that is so cheap that I dont mind throwing the whole kit away after
> doing a port or two, rather than trying to create something that is  
> good
> forever.

The "SPD" solution works over all families of DIMMs.

>>> I think that we are going into a world where we have to figure out
>>> usb debug port.
>> It's certainly one good debugging option but maybe not the only good
>> one.
> Especially it does not help for reflashing. Finding something nifty  
> here
> would be nice.

JTAG into the north bridge, and you can init all system buses, done ;-)

On some systems you don't even need such init, the PCI starts running --
so you can DMA from a plug-in card to the flash chip.

Again though: none of this is suitable for an "end-user", someone not
too hardware savvy to help getting LinuxBIOS going on his board (or to
restore flash after an "accident", etc).


More information about the coreboot mailing list