[BULK] RE: [LinuxBIOS] FYI: AMD support for cache as ram.

[Li-Ta Lo]

On Mon, 2005-06-06 at 21:02 -0700, yhlu wrote:
> I just figure out, the ss don't need to be changed. and only need to
> set the esp.
> 
> It can get into amd64_main in failover.
> 
> the it seems even the 64 range in cache can be read and write, but the
> result is not right. It means when clear all of range, the readout
> will still be 0xff....
> 
>  #if 1
>         movl    $CacheBase, %edi
>         cld
>         movl    $04000, %ecx
>         xorl    %eax, %eax
>         rep     stosl
>  #endif
>         movl  $CacheBase, %esi
>         movl (%esi), %eax
> .testx:        outb %al, $0x80
>          jmp .testx
>  
>         intel_chip_post_macro(0x22)     /* post 22 */
>  

The AMD doc says you have to use REP MOVS to read from IO space. It 
looks like you are using REP STOS.

> Ollie,
>       are you sure that your code can use 300 bytes in cache?
> 

Yea, I am sure it uses less than 448 bytes.

You didn't reuse the ldscript and .inc files in the .tgz I sent, right?

> YH
-- 
Li-Ta Lo <ollie at lanl.gov>
Los Alamos National Lab